Merge remote-tracking branch 'u-boot-ti/master'

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / cpu_init.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index d7e80fc5122e364bef7380ce72eb1819e4f9be8b..736293c41d290b7ecc79857fd138b075dbbf7b7a 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -38,6 +38,7 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_srio.h>
+#include <hwconfig.h>
 #include <linux/compiler.h>
 #include "mp.h"
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
@@ -294,6 +295,43 @@ static void __fsl_serdes__init(void)
 }
 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+int enable_cluster_l2(void)
+{
+       int i = 0;
+       u32 cluster;
+       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       struct ccsr_cluster_l2 __iomem *l2cache;
+
+       cluster = in_be32(&gur->tp_cluster[i].lower);
+       if (cluster & TP_CLUSTER_EOC)
+               return 0;
+
+       /* The first cache has already been set up, so skip it */
+       i++;
+
+       /* Look through the remaining clusters, and set up their caches */
+       do {
+               l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+               cluster = in_be32(&gur->tp_cluster[i].lower);
+
+               /* set stash ID to (cluster) * 2 + 32 + 1 */
+               clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
+
+               printf("enable l2 for cluster %d %p\n", i, l2cache);
+
+               out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
+               while ((in_be32(&l2cache->l2csr0) &
+                       (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
+                       ;
+               out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+               i++;
+       } while (!(cluster & TP_CLUSTER_EOC));
+
+       return 0;
+}
+#endif
+
 /*
  * Initialize L2 as cache.
  *
@@ -305,11 +343,52 @@ int cpu_init_r(void)
 {
        __maybe_unused u32 svr = get_svr();
 #ifdef CONFIG_SYS_LBC_LCRR
-       volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+       fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
+#endif
+#ifdef CONFIG_L2_CACHE
+       ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+       struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
 #endif
 
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
-       if (SVR_MAJ(svr) < 3) {
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
+       defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
+       /*
+        * CPU22 and NMG_CPU_A011 share the same workaround.
+        * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+        * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+        * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
+        * fixed in 2.0. NMG_CPU_A011 is activated by default and can
+        * be disabled by hwconfig with syntax:
+        *
+        * fsl_cpu_a011:disable
+        */
+       extern int enable_cpu_a011_workaround;
+#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
+       enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
+#else
+       char buffer[HWCONFIG_BUFFER_SIZE];
+       char *buf = NULL;
+       int n, res;
+
+       n = getenv_f("hwconfig", buffer, sizeof(buffer));
+       if (n > 0)
+               buf = buffer;
+
+       res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
+       if (res > 0)
+               enable_cpu_a011_workaround = 0;
+       else {
+               if (n >= HWCONFIG_BUFFER_SIZE) {
+                       printf("fsl_cpu_a011 was not found. hwconfig variable "
+                               "may be too long\n");
+               }
+               enable_cpu_a011_workaround =
+                       (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
+                       (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
+       }
+#endif
+       if (enable_cpu_a011_workaround) {
                flush_dcache();
                mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
                sync();
@@ -319,7 +398,6 @@ int cpu_init_r(void)
        puts ("L2:    ");
 
 #if defined(CONFIG_L2_CACHE)
-       volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
        volatile uint cache_ctl;
        uint ver;
        u32 l2siz_field;
@@ -430,6 +508,11 @@ int cpu_init_r(void)
        }
 
 skip_l2:
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+       if (l2cache->l2csr0 & L2CSR0_L2E)
+               printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
+
+       enable_cluster_l2();
 #else
        puts("disabled\n");
 #endif
@@ -441,11 +524,18 @@ skip_l2:
 
 #ifdef CONFIG_SYS_SRIO
        srio_init();
-#ifdef CONFIG_SRIOBOOT_MASTER
-       srio_boot_master();
-#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
-       srio_boot_master_release_slave();
-#endif
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 
+       char *s = getenv("bootmaster");
+       if (s) {
+               if (!strcmp(s, "SRIO1")) {
+                       srio_boot_master(1);
+                       srio_boot_master_release_slave(1);
+               }
+               if (!strcmp(s, "SRIO2")) {
+                       srio_boot_master(2);
+                       srio_boot_master_release_slave(2);
+               }
+       }
 #endif
 #endif
 
@@ -453,11 +543,13 @@ skip_l2:
        setup_mp();
 #endif
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
        {
-               void *p;
-               p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
-               setbits_be32(p, 1 << (31 - 14));
+               if (SVR_MAJ(svr) < 3) {
+                       void *p;
+                       p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+                       setbits_be32(p, 1 << (31 - 14));
+               }
        }
 #endif