Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / fsl_corenet_serdes.c

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 2a6806036975673e5d504043211577a324ca69e7..b621adf4af516bb9e5599bd0ce675af0437fb64b 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -92,10 +92,21 @@ static const struct {
        { 17, 163, FSL_SRDS_BANK_2 },
        { 18, 164, FSL_SRDS_BANK_2 },
        { 19, 165, FSL_SRDS_BANK_2 },
+#ifdef CONFIG_PPC_P4080
        { 20, 170, FSL_SRDS_BANK_3 },
        { 21, 171, FSL_SRDS_BANK_3 },
        { 22, 172, FSL_SRDS_BANK_3 },
        { 23, 173, FSL_SRDS_BANK_3 },
+#else
+       { 20, 166, FSL_SRDS_BANK_3 },
+       { 21, 167, FSL_SRDS_BANK_3 },
+       { 22, 168, FSL_SRDS_BANK_3 },
+       { 23, 169, FSL_SRDS_BANK_3 },
+#endif
+#if SRDS_MAX_BANK > 3
+       { 24, 175, FSL_SRDS_BANK_4 },
+       { 25, 176, FSL_SRDS_BANK_4 },
+#endif
 };
 
 int serdes_get_lane_idx(int lane)
@@ -482,7 +493,7 @@ static void wait_for_rstdone(unsigned int bank)
 }
 
 
-void __soc_serdes_init(void)
+static void __soc_serdes_init(void)
 {
        /* Allow for SoC-specific initialization in <SOC>_serdes.c  */
 };
@@ -493,6 +504,9 @@ void fsl_serdes_init(void)
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        int cfg;
        serdes_corenet_t *srds_regs;
+#ifdef CONFIG_PPC_P5040
+       serdes_corenet_t *srds2_regs;
+#endif
        int lane, bank, idx;
        int have_bank[SRDS_MAX_BANK] = {};
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -503,7 +517,7 @@ void fsl_serdes_init(void)
        size_t arglen;
 #endif
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
-       int need_serdes_a001;   /* TRUE == need work-around for SERDES A001 */
+       int need_serdes_a001;   /* true == need work-around for SERDES A001 */
 #endif
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
        char buffer[HWCONFIG_BUFFER_SIZE];
@@ -574,6 +588,34 @@ void fsl_serdes_init(void)
                }
        }
 
+#ifdef CONFIG_PPC_P5040
+       /*
+        * Lanes on bank 4 on P5040 are commented-out, but for some SERDES
+        * protocols, these lanes are routed to SATA.  We use serdes_prtcl_map
+        * to decide whether a protocol is supported on a given lane, so SATA
+        * will be identified as not supported, and therefore not initialized.
+        * So for protocols which use SATA on bank4, we add SATA support in
+        * serdes_prtcl_map.
+        */
+       switch (cfg) {
+       case 0x0:
+       case 0x1:
+       case 0x2:
+       case 0x3:
+       case 0x4:
+       case 0x5:
+       case 0x6:
+       case 0x7:
+               serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
+               break;
+       default:
+               srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+
+               /* We don't need bank 4, so power it down */
+               setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
+       }
+#endif
+
        soc_serdes_init();
 
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -617,6 +659,38 @@ void fsl_serdes_init(void)
                }
        }
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004699
+       /*
+        * To avoid the situation that resulted in the P4080 erratum
+        * SERDES-8, a given SerDes bank will use the PLLs from the previous
+        * bank if one of the PLL frequencies is a multiple of the other.  For
+        * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz,
+        * then bank 3 will use bank 2's PLL.  P5040 Erratum A-004699 says
+        * that, in this situation, lane synchronization is not initiated.  So
+        * when we detect a bank with a "borrowed" PLL, we have to manually
+        * initiate lane synchronization.
+        */
+       for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) {
+               /* Determine the first lane for this bank */
+               unsigned int lane;
+
+               for (lane = 0; lane < SRDS_MAX_LANES; lane++)
+                       if (lanes[lane].bank == bank)
+                               break;
+               idx = lanes[lane].idx;
+
+               /*
+                * Check if the PLL for the bank is borrowed.  The UOTHL
+                * bit of the first lane will tell us that.
+                */
+               if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) {
+                       /* Manually start lane synchronization */
+                       setbits_be32(&srds_regs->bank[bank].pllcr0,
+                                    SRDS_PLLCR0_PVCOCNT_EN);
+               }
+       }
+#endif
+
 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
        for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
                enum srds_prtcl lane_prtcl;
@@ -644,9 +718,13 @@ void fsl_serdes_init(void)
 
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
                /*
-                * Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for
-                * each of the SerDes lanes selected as SGMII, XAUI, SRIO, or
-                * AURORA before the device is initialized.
+                * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1
+                * for each of the SerDes lanes selected as SGMII, XAUI, SRIO,
+                * or AURORA before the device is initialized.
+                *
+                * Note that this part of the SERDES-9 work-around is
+                * redundant if the work-around for A-4580 has already been
+                * applied via PBI.
                 */
                switch (lane_prtcl) {
                case SGMII_FM1_DTSEC1:
@@ -663,10 +741,12 @@ void fsl_serdes_init(void)
                case SRIO1:
                case SRIO2:
                case AURORA:
-                       clrsetbits_be32(&srds_regs->lane[idx].ttlcr0,
-                                       SRDS_TTLCR0_FLT_SEL_MASK,
-                                       SRDS_TTLCR0_FLT_SEL_750PPM |
-                                       SRDS_TTLCR0_PM_DIS);
+                       out_be32(&srds_regs->lane[idx].ttlcr0,
+                                SRDS_TTLCR0_FLT_SEL_KFR_26 |
+                                SRDS_TTLCR0_FLT_SEL_KPH_28 |
+                                SRDS_TTLCR0_FLT_SEL_750PPM |
+                                SRDS_TTLCR0_FREQOVD_EN);
+                       break;
                default:
                        break;
                }