volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_CORENET
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
+ unsigned int cpu;
const u8 core_cplx_PLL[16] = {
[ 0] = 0, /* CC1 PPL / 1 */
freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
}
rcw_tmp = in_be32(&gur->rcwsr[3]);
- for (i = 0; i < cpu_numcores(); i++) {
- u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
+ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
+ u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
u32 cplx_pll = core_cplx_PLL[c_pll_sel];
- sysInfo->freqProcessor[i] =
+ sysInfo->freqProcessor[cpu] =
freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
}
#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
#define HWA_CC_PLL 1
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
-#define HWA_CC_PLL 2
+#define HWA_CC_PLL 2
#else
#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
#endif
#endif
#ifdef CONFIG_QE
-#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
- defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
sysInfo->freqQE = sysInfo->freqSystemBus;
#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)