* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
/*
* Each cluster has up to 4 cores, sharing the same PLL selection.
- * The cluster assignment is fixed per SoC. There is no way identify the
- * assignment so far, presuming the "first configuration" which is to
- * fill the lower cluster group first before moving up to next group.
- * PLL1, PLL2, PLL3 are cluster group A, feeding core 0~3 on cluster 1
- * and core 4~7 on cluster 2
- * PLL4, PLL5, PLL6 are cluster group B, feeding core 8~11 on cluster 3
- * and core 12~15 on cluster 4 if existing
+ * The cluster assignment is fixed per SoC. PLL1, PLL2, PLL3 are
+ * cluster group A, feeding cores on cluster 1 and cluster 2.
+ * PLL4, PLL5, PLL6 are cluster group B, feeding cores on cluster 3
+ * and cluster 4 if existing.
*/
for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
- u32 c_pll_sel = (in_be32(&clk->clkc0csr + (cpu / 4) * 8) >> 27)
+ int cluster = fsl_qoriq_core_to_cluster(cpu);
+ u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
& 0xf;
u32 cplx_pll = core_cplx_PLL[c_pll_sel];
if (cplx_pll > 3)
printf("Unsupported architecture configuration"
" in function %s\n", __func__);
- cplx_pll += (cpu / 8) * 3;
-
+ cplx_pll += (cluster / 2) * 3;
sysInfo->freqProcessor[cpu] =
freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
}
+#ifdef CONFIG_PPC_B4860
+#define FM1_CLK_SEL 0xe0000000
+#define FM1_CLK_SHIFT 29
+#else
#define PME_CLK_SEL 0xe0000000
#define PME_CLK_SHIFT 29
#define FM1_CLK_SEL 0x1c000000
#define FM1_CLK_SHIFT 26
+#endif
rcw_tmp = in_be32(&gur->rcwsr[7]);
#ifdef CONFIG_SYS_DPAA_PME
case 4:
sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
break;
+ case 5:
+ sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
+ break;
case 6:
sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
break;
#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
- u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
+ u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
+ & 0xf;
u32 cplx_pll = core_cplx_PLL[c_pll_sel];
sysInfo->freqProcessor[cpu] =
#endif
#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
+#endif
+
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#else /* CONFIG_FSL_CORENET */
gd->cpu_clk = sys_info.freqProcessor[0];
gd->bus_clk = sys_info.freqSystemBus;
gd->mem_clk = sys_info.freqDDRBus;
- gd->lbc_clk = sys_info.freqLocalBus;
+ gd->arch.lbc_clk = sys_info.freqLocalBus;
#ifdef CONFIG_QE
- gd->qe_clk = sys_info.freqQE;
- gd->brg_clk = gd->qe_clk / 2;
+ gd->arch.qe_clk = sys_info.freqQE;
+ gd->arch.brg_clk = gd->arch.qe_clk / 2;
#endif
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,
*/
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
- gd->i2c1_clk = sys_info.freqSystemBus;
+ gd->arch.i2c1_clk = sys_info.freqSystemBus;
#elif defined(CONFIG_MPC8544)
/*
* On the 8544, the I2C clock is the same as the SEC clock. This can be
* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
*/
if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
- gd->i2c1_clk = sys_info.freqSystemBus / 3;
+ gd->arch.i2c1_clk = sys_info.freqSystemBus / 3;
else
- gd->i2c1_clk = sys_info.freqSystemBus / 2;
+ gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
#else
/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
- gd->i2c1_clk = sys_info.freqSystemBus / 2;
+ gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
#endif
- gd->i2c2_clk = gd->i2c1_clk;
+ gd->arch.i2c2_clk = gd->arch.i2c1_clk;
#if defined(CONFIG_FSL_ESDHC)
#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
defined(CONFIG_P1014)
- gd->sdhc_clk = gd->bus_clk;
+ gd->arch.sdhc_clk = gd->bus_clk;
#else
- gd->sdhc_clk = gd->bus_clk / 2;
+ gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif
#endif /* defined(CONFIG_FSL_ESDHC) */
#if defined(CONFIG_CPM2)
- gd->vco_out = 2*sys_info.freqSystemBus;
- gd->cpm_clk = gd->vco_out / 2;
- gd->scc_clk = gd->vco_out / 4;
- gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
+ gd->arch.vco_out = 2*sys_info.freqSystemBus;
+ gd->arch.cpm_clk = gd->arch.vco_out / 2;
+ gd->arch.scc_clk = gd->arch.vco_out / 4;
+ gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
#endif
if(gd->cpu_clk != 0) return (0);
projects / karo-tx-uboot.git / blobdiff