Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / t4240_serdes.c

diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index c001780ca969c5cacd06d734e252d666f48627ea..74c4c81887c2b66507aef51ea2d761dd2a056e71 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -1,23 +1,7 @@
 /*
  * Copyright 2012 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -46,22 +30,41 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
                HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
                HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
                HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+       {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
        {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
                SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+       {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
        {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
                SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+       {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+               NONE, NONE, QSGMII_FM1_A, NONE} },
        {38, {NONE, NONE, QSGMII_FM1_B, NONE,
                NONE, NONE, QSGMII_FM1_A, NONE}},
+       {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               NONE, NONE, QSGMII_FM1_A, NONE} },
        {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
                NONE, NONE, QSGMII_FM1_A, NONE}},
+       {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               NONE, NONE, QSGMII_FM1_A, NONE} },
        {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
                NONE, NONE, QSGMII_FM1_A, NONE}},
+       {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               NONE, NONE, QSGMII_FM1_A, NONE} },
        {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
                NONE, NONE, QSGMII_FM1_A, NONE}},
@@ -81,10 +84,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
                HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+       {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -93,10 +104,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -105,6 +124,10 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -113,34 +136,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {37, {NONE, NONE, QSGMII_FM2_B, NONE,
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {38, {NONE, NONE, QSGMII_FM2_B, NONE,
-               NONE, NONE, QSGMII_FM1_A, NONE}},
+               NONE, NONE, QSGMII_FM2_A, NONE} },
+       {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               NONE, NONE, QSGMII_FM1_A, NONE}},
+               NONE, NONE, QSGMII_FM2_A, NONE} },
+       {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               NONE, NONE, QSGMII_FM1_A, NONE}},
+               NONE, NONE, QSGMII_FM2_A, NONE} },
+       {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-               NONE, NONE, QSGMII_FM1_A, NONE}},
+               NONE, NONE, QSGMII_FM2_A, NONE} },
+       {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-               NONE, NONE, QSGMII_FM1_A, NONE}},
+               NONE, NONE, QSGMII_FM2_A, NONE} },
+       {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               NONE, NONE, QSGMII_FM1_A, NONE}},
+               NONE, NONE, QSGMII_FM2_A, NONE} },
+       {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               NONE, NONE, QSGMII_FM2_A, NONE} },
        {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-               NONE, NONE, QSGMII_FM1_A, NONE}},
+               NONE, NONE, QSGMII_FM2_A, NONE} },
+       {55, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+               XFI_FM2_MAC10, XFI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
                XFI_FM2_MAC10, XFI_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -153,22 +208,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 };
 static const struct serdes_config serdes3_cfg_tbl[] = {
        /* SerDes 3 */
+       {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
        {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
+       {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
        {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
+       {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
        {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
+       {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
        {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
        {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
        {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+       {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               PCIE2, PCIE2, PCIE2, PCIE2} },
        {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                PCIE2, PCIE2, PCIE2, PCIE2}},
+       {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               PCIE2, PCIE2, PCIE2, PCIE2} },
        {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                PCIE2, PCIE2, PCIE2, PCIE2}},
+       {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               SRIO1, SRIO1, SRIO1, SRIO1} },
        {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                SRIO1, SRIO1, SRIO1, SRIO1}},
        {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                SRIO1, SRIO1, SRIO1, SRIO1}},
+       {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               SRIO1, SRIO1, SRIO1, SRIO1} },
        {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                SRIO1, SRIO1, SRIO1, SRIO1}},
        {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -177,18 +244,26 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
 };
 static const struct serdes_config serdes4_cfg_tbl[] = {
        /* SerDes 4 */
+       {1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} },
        {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
+       {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
        {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
+       {5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
        {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+       {7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
        {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+       {9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
        {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
+       {11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
        {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
+       {13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
        {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+       {15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
        {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
        {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
        {}
 };
-#elif defined(CONFIG_PPC_T4160)
+#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
 static const struct serdes_config serdes1_cfg_tbl[] = {
        /* SerDes 1 */
        {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
@@ -203,36 +278,66 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
                HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
                HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
                HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
+       {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
        {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
                SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+       {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
        {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
                SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+       {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+               NONE, NONE, QSGMII_FM1_A, NONE} },
        {38, {NONE, NONE, QSGMII_FM1_B, NONE,
                NONE, NONE, QSGMII_FM1_A, NONE} },
        {}
 };
 static const struct serdes_config serdes2_cfg_tbl[] = {
        /* SerDes 2 */
+       {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -241,34 +346,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                NONE, NONE} },
+       {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
                SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {37, {NONE, NONE, QSGMII_FM2_B, NONE,
+               NONE, QSGMII_FM1_A, NONE, NONE} },
        {38, {NONE, NONE, QSGMII_FM2_B, NONE,
                NONE, QSGMII_FM1_A, NONE, NONE} },
+       {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, QSGMII_FM1_A, NONE, NONE} },
        {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                NONE, QSGMII_FM1_A, NONE, NONE} },
+       {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, QSGMII_FM1_A, NONE, NONE} },
        {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                NONE, QSGMII_FM1_A, NONE, NONE} },
+       {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, QSGMII_FM1_A, NONE, NONE} },
        {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
                SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
                NONE, QSGMII_FM1_A, NONE, NONE} },
+       {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               NONE, NONE, NONE, NONE} },
        {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                XAUI_FM2_MAC9, XAUI_FM2_MAC9,
                NONE, NONE, NONE, NONE} },
+       {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               NONE, NONE, NONE, NONE} },
        {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                NONE, NONE, NONE, NONE} },
+       {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               NONE, NONE, NONE, NONE} },
        {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
                NONE, NONE, NONE, NONE} },
+       {55, {NONE, XFI_FM1_MAC10,
+               XFI_FM2_MAC10, NONE,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
        {56, {NONE, XFI_FM1_MAC10,
                XFI_FM2_MAC10, NONE,
                SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -281,22 +418,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 };
 static const struct serdes_config serdes3_cfg_tbl[] = {
        /* SerDes 3 */
+       {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
        {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+       {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
        {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
+       {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
        {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+       {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
        {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
        {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
        {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
+       {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               PCIE2, PCIE2, PCIE2, PCIE2} },
        {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                PCIE2, PCIE2, PCIE2, PCIE2} },
+       {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               PCIE2, PCIE2, PCIE2, PCIE2} },
        {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                PCIE2, PCIE2, PCIE2, PCIE2} },
+       {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               SRIO1, SRIO1, SRIO1, SRIO1} },
        {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                SRIO1, SRIO1, SRIO1, SRIO1} },
        {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                SRIO1, SRIO1, SRIO1, SRIO1} },
+       {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               SRIO1, SRIO1, SRIO1, SRIO1} },
        {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
                SRIO1, SRIO1, SRIO1, SRIO1} },
        {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -305,12 +454,19 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
 };
 static const struct serdes_config serdes4_cfg_tbl[] = {
        /* SerDes 4 */
+       {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
        {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
+       {5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
        {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+       {7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
        {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+       {9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
        {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
+       {11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
        {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
+       {13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
        {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
+       {15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
        {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
        {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
        {}