Merge remote-tracking branch 'u-boot-ti/master'

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc8xxx / ddr / lc_common_dimm_params.c

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index 00f3d6c600a322206372a33908ccc67d5ed30ce4..6a1f4e4e38638072c03bc8ff6aaa398255dee04d 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -27,8 +27,10 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
 
        /* compute the common CAS latency supported between slots */
        tmp = dimm_params[0].caslat_X;
-       for (i = 1; i < number_of_dimms; i++)
-                tmp &= dimm_params[i].caslat_X;
+       for (i = 1; i < number_of_dimms; i++) {
+               if (dimm_params[i].n_ranks)
+                       tmp &= dimm_params[i].caslat_X;
+       }
        common_caslat = tmp;
 
        /* compute the max tAAmin tCKmin between slots */
@@ -38,9 +40,9 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
        }
        /* validate if the memory clk is in the range of dimms */
        if (mclk_ps < tCKmin_X_ps) {
-               printf("The DIMM max tCKmin is %d ps,"
-                       "doesn't support the MCLK cycle %d ps\n",
-                       tCKmin_X_ps, mclk_ps);
+               printf("DDR clock (MCLK cycle %u ps) is faster than "
+                       "the slowest DIMM(s) (tCKmin %u ps) can support.\n",
+                       mclk_ps, tCKmin_X_ps);
                return 1;
        }
        /* determine the acutal cas latency */
@@ -74,7 +76,7 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
 unsigned int
 compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
                                      common_timing_params_t *outpdimm,
-                                     unsigned int number_of_dimms)
+                                     const unsigned int number_of_dimms)
 {
        unsigned int i, j;
 
@@ -124,13 +126,20 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
                        temp1++;
                        continue;
                }
+
+               /*
+                * check if quad-rank DIMM is plugged if
+                * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined
+                * Only the board with proper design is capable
+                */
+#ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
                if (dimm_params[i].n_ranks == 4 && \
                  CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
                        printf("Found Quad-rank DIMM, not able to support.");
                        temp1++;
                        continue;
                }
-
+#endif
                /*
                 * Find minimum tCKmax_ps to find fastest slow speed,
                 * i.e., this is the slowest the whole system can go.
@@ -234,11 +243,14 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
        if (outpdimm->all_DIMMs_registered)
                for (j = 0; j < 16; j++) {
                        outpdimm->rcw[j] = dimm_params[0].rcw[j];
-                       for (i = 1; i < number_of_dimms; i++)
+                       for (i = 1; i < number_of_dimms; i++) {
+                               if (!dimm_params[i].n_ranks)
+                                       continue;
                                if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
                                        temp1 = 1;
                                        break;
                                }
+                       }
                }
 
        if (temp1 != 0)
@@ -448,7 +460,8 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 
 #if defined(CONFIG_FSL_DDR2)
        if (lowest_good_caslat < 4) {
-               additive_latency = picos_to_mclk(tRCD_ps) - lowest_good_caslat;
+               additive_latency = (picos_to_mclk(tRCD_ps) > lowest_good_caslat)
+                       ? picos_to_mclk(tRCD_ps) - lowest_good_caslat : 0;
                if (mclk_to_picos(additive_latency) > tRCD_ps) {
                        additive_latency = picos_to_mclk(tRCD_ps);
                        debug("setting additive_latency to %u because it was "
@@ -490,5 +503,15 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
         */
        outpdimm->additive_latency = additive_latency;
 
+       debug("tCKmin_ps = %u\n", outpdimm->tCKmin_X_ps);
+       debug("tRCD_ps   = %u\n", outpdimm->tRCD_ps);
+       debug("tRP_ps    = %u\n", outpdimm->tRP_ps);
+       debug("tRAS_ps   = %u\n", outpdimm->tRAS_ps);
+       debug("tWR_ps    = %u\n", outpdimm->tWR_ps);
+       debug("tWTR_ps   = %u\n", outpdimm->tWTR_ps);
+       debug("tRFC_ps   = %u\n", outpdimm->tRFC_ps);
+       debug("tRRD_ps   = %u\n", outpdimm->tRRD_ps);
+       debug("tRC_ps    = %u\n", outpdimm->tRC_ps);
+
        return 0;
 }