ppc4xx: Remove 4xx NAND booting support

[karo-tx-uboot.git] / arch / powerpc / cpu / ppc4xx / start.S

diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index e72c37c75ba011fb4ca76ba3c9312cf099c7ed96..11b55d5a56e4ba44ebe527eacae162cbe5a818a5 100644 (file)
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -182,16 +182,13 @@
 
 
        .extern ext_bus_cntlr_init
-#ifdef CONFIG_NAND_U_BOOT
-       .extern reconfig_tlb0
-#endif
 
 /*
  * Set up GOT: Global Offset Table
  *
  * Use r12 to access the GOT
  */
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD)
        START_GOT
        GOT_ENTRY(_GOT2_TABLE_)
        GOT_ENTRY(_FIXUP_TABLE_)
@@ -205,22 +202,7 @@
        GOT_ENTRY(__bss_end)
        GOT_ENTRY(__bss_start)
        END_GOT
-#endif /* CONFIG_NAND_SPL */
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
-       !defined(CONFIG_SPL_BUILD)
-       /*
-        * NAND U-Boot image is started from offset 0
-        */
-       .text
-#if defined(CONFIG_440)
-       bl      reconfig_tlb0
-#endif
-       GET_GOT
-       bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
-       bl      board_init_f
-       /* NOTREACHED - board_init_f() does not return */
-#endif
+#endif /* CONFIG_SPL_BUILD */
 
 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
        /*
@@ -255,9 +237,7 @@
  */
 
 #if defined(CONFIG_440)
-#if !defined(CONFIG_NAND_SPL)
     .section .bootpg,"ax"
-#endif
     .globl _start_440
 
 /**************************************************************************/
@@ -511,7 +491,7 @@ tlbnx2:     addi    r4,r4,1         /* Next TLB */
  * r3 - 1st arg to board_init(): IMMP pointer
  * r4 - 2nd arg to board_init(): boot flag
  */
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD)
        .text
        .long   0x27051956              /* U-Boot Magic Number                  */
        .globl  version_string
@@ -777,9 +757,6 @@ _start:
        stwu    r1,-8(r1)               /* Save back chain and move SP */
        stw     r0,+12(r1)              /* Save return addr (underflow vect) */
 
-#ifdef CONFIG_NAND_SPL
-       bl      nand_boot_common        /* will not return */
-#else
 #ifndef CONFIG_SPL_BUILD
        GET_GOT
 #endif
@@ -787,7 +764,6 @@ _start:
        bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
        bl      board_init_f
        /* NOTREACHED - board_init_f() does not return */
-#endif
 
 #endif /* CONFIG_440 */
 
@@ -1050,9 +1026,6 @@ _start:
        stw     r0, +12(r1)             /* Save return addr (underflow vect) */
 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
 
-#ifdef CONFIG_NAND_SPL
-       bl      nand_boot_common        /* will not return */
-#else
        GET_GOT                 /* initialize GOT access                        */
 
        bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
@@ -1060,13 +1033,11 @@ _start:
        bl      board_init_f    /* run first part of init code (from Flash)     */
        /* NOTREACHED - board_init_f() does not return */
 
-#endif /* CONFIG_NAND_SPL */
-
 #endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
        /*----------------------------------------------------------------------- */
 
 
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD)
 /*
  * This code finishes saving the registers to the exception frame
  * and jumps to the appropriate handler for the exception.
@@ -1632,7 +1603,7 @@ __440_msr_continue:
        blr
        function_epilog(dcbz_area)
 #endif /* CONFIG_440 */
-#endif /* CONFIG_NAND_SPL */
+#endif /* CONFIG_SPL_BUILD */
 
 /*------------------------------------------------------------------------------- */
 /* Function:    in8 */
@@ -1981,75 +1952,3 @@ pll_wait:
        blr
        function_epilog(mftlb1)
 #endif /* CONFIG_440 */
-
-#if defined(CONFIG_NAND_SPL)
-/*
- * void nand_boot_relocate(dst, src, bytes)
- *
- * r3 = Destination address to copy code to (in SDRAM)
- * r4 = Source address to copy code from
- * r5 = size to copy in bytes
- */
-nand_boot_relocate:
-       mr      r6,r3
-       mr      r7,r4
-       mflr    r8
-
-       /*
-        * Copy SPL from icache into SDRAM
-        */
-       subi    r3,r3,4
-       subi    r4,r4,4
-       srwi    r5,r5,2
-       mtctr   r5
-..spl_loop:
-       lwzu    r0,4(r4)
-       stwu    r0,4(r3)
-       bdnz    ..spl_loop
-
-       /*
-        * Calculate "corrected" link register, so that we "continue"
-        * in execution in destination range
-        */
-       sub     r3,r7,r6        /* r3 = src - dst */
-       sub     r8,r8,r3        /* r8 = link-reg - (src - dst) */
-       mtlr    r8
-       blr
-
-nand_boot_common:
-       /*
-        * First initialize SDRAM. It has to be available *before* calling
-        * nand_boot().
-        */
-       lis     r3,CONFIG_SYS_SDRAM_BASE@h
-       ori     r3,r3,CONFIG_SYS_SDRAM_BASE@l
-       bl      initdram
-
-       /*
-        * Now copy the 4k SPL code into SDRAM and continue execution
-        * from there.
-        */
-       lis     r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
-       ori     r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
-       lis     r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
-       ori     r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
-       lis     r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
-       ori     r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
-       bl      nand_boot_relocate
-
-       /*
-        * We're running from SDRAM now!!!
-        *
-        * It is necessary for 4xx systems to relocate from running at
-        * the original location (0xfffffxxx) to somewhere else (SDRAM
-        * preferably). This is because CS0 needs to be reconfigured for
-        * NAND access. And we can't reconfigure this CS when currently
-        * "running" from it.
-        */
-
-       /*
-        * Finally call nand_boot() to load main NAND U-Boot image from
-        * NAND and jump to it.
-        */
-       bl      nand_boot               /* will not return */
-#endif /* CONFIG_NAND_SPL */