Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / arch / powerpc / include / asm / fsl_pci.h

diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index c740da37ce3b346e5d627af9560735fbcf5e5a7b..749411c1016234a0ac7420f3ffb994796f102d83 100644 (file)
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2012 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -13,6 +13,34 @@
 
 #define PEX_IP_BLK_REV_2_2     0x02080202
 #define PEX_IP_BLK_REV_2_3     0x02080203
+#define PEX_IP_BLK_REV_3_0     0x02080300
+
+/* Freescale-specific PCI config registers */
+#define FSL_PCI_PBFR           0x44
+
+#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
+/* Currently only the PCIe capability is used, so hardcode the offset.
+ * if more capabilities need to be justified, the capability link method
+ * should be applied here
+ */
+#define FSL_PCIE_CAP_ID                0x70
+#define PCI_DCR                0x78    /* PCIe Device Control Register */
+#define PCI_DSR                0x7a    /* PCIe Device Status Register */
+#define PCI_LSR                0x82    /* PCIe Link Status Register */
+#define PCI_LCR                0x80    /* PCIe Link Control Register */
+#else
+#define FSL_PCIE_CAP_ID                0x4c
+#define PCI_DCR                0x54    /* PCIe Device Control Register */
+#define PCI_DSR                0x56    /* PCIe Device Status Register */
+#define PCI_LSR                0x5e    /* PCIe Link Status Register */
+#define PCI_LCR                0x5c    /* PCIe Link Control Register */
+#endif
+
+#define FSL_PCIE_CFG_RDY       0x4b0
+#define FSL_PROG_IF_AGENT      0x1
+
+#define PCI_LTSSM      0x404   /* PCIe Link Training, Status State Machine */
+#define  PCI_LTSSM_L0  0x16    /* L0 state */
 
 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
 int fsl_is_pci_agent(struct pci_controller *hose);
@@ -149,7 +177,10 @@ typedef struct ccsr_pci {
        u32     perr_cap3;      /* 0xe34 - PCIE Error Capture Register 3 */
        char    res23[200];
        u32     pdb_stat;       /* 0xf00 - PCIE Debug Status */
-       char    res24[252];
+       char    res24[16];
+       u32     pex_csr0;       /* 0xf14 - PEX Control/Status register 0*/
+       u32     pex_csr1;       /* 0xf18 - PEX Control/Status register 1*/
+       char    res25[228];
 } ccsr_fsl_pci_t;
 #define PCIE_CONFIG_PC 0x00020000
 #define PCIE_CONFIG_OB_CK      0x00002000