Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

[karo-tx-uboot.git] / arch / powerpc / include / asm / immap_512x.h

diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h
index 95350fd9b84d672f08d56fd51afa90b90fc7ae48..824821981df467ca41a06716162c2b5b83f231eb 100644 (file)
--- a/arch/powerpc/include/asm/immap_512x.h
+++ b/arch/powerpc/include/asm/immap_512x.h
@@ -227,7 +227,9 @@ typedef struct clk512x {
 #define CLOCK_SCCR2_IIM_EN             0x00080000
 
 /* SCFR1 System Clock Frequency Register 1 */
+#ifndef SCFR1_IPS_DIV
 #define SCFR1_IPS_DIV          0x3
+#endif
 #define SCFR1_IPS_DIV_MASK     0x03800000
 #define SCFR1_IPS_DIV_SHIFT    23
 
@@ -238,6 +240,12 @@ typedef struct clk512x {
 #define SCFR1_LPC_DIV_MASK     0x00003800
 #define SCFR1_LPC_DIV_SHIFT    11
 
+#define SCFR1_NFC_DIV_MASK     0x00000700
+#define SCFR1_NFC_DIV_SHIFT    8
+
+#define SCFR1_DIU_DIV_MASK     0x000000FF
+#define SCFR1_DIU_DIV_SHIFT    0
+
 /* SCFR2 System Clock Frequency Register 2 */
 #define SCFR2_SYS_DIV          0xFC000000
 #define SCFR2_SYS_DIV_SHIFT    26
@@ -343,6 +351,7 @@ typedef struct ddr512x {
 
 /* MDDRC SYS CFG and Timing CFG0 Registers */
 #define MDDRC_SYS_CFG_EN       0xF0000000
+#define MDDRC_SYS_CFG_CKE_MASK 0x40000000
 #define MDDRC_SYS_CFG_CMD_MASK 0x10000000
 #define MDDRC_REFRESH_ZERO_MASK        0x0000FFFF
 
@@ -356,6 +365,11 @@ typedef struct ddr512x_config {
        u32 ddr_time_config2;   /* Timing Configuration Register */
 } ddr512x_config_t;
 
+typedef struct sdram_conf_s {
+       unsigned long size;
+       ddr512x_config_t cfg;
+} sdram_conf_t;
+
 /*
  * DMA/Messaging Unit
  */
@@ -848,10 +862,6 @@ typedef struct ioctrl512x {
        u8      reserved[0x0cfc];               /* fill to 4096 bytes size */
 } ioctrl512x_t;
 
-/* Indexes in regs array */
-/* Set for DDR */
-#define IOCTRL_MUX_DDR         0x00000036
-
 /* IO pin fields */
 #define IO_PIN_FMUX(v) ((v) << 7)      /* pin function */
 #define IO_PIN_HOLD(v) ((v) << 5)      /* hold time, pci only */
@@ -869,6 +879,19 @@ typedef struct iopin_t {
 
 void iopin_initialize(iopin_t *,int);
 
+/*
+ * support to adjust individual parts of the IO pin setup
+ */
+
+#define IO_PIN_OVER_EACH       (1 << 0) /* for compatibility */
+#define IO_PIN_OVER_FMUX       (1 << 1)
+#define IO_PIN_OVER_HOLD       (1 << 2)
+#define IO_PIN_OVER_PULL       (1 << 3)
+#define IO_PIN_OVER_STRIG      (1 << 4)
+#define IO_PIN_OVER_DRVSTR     (1 << 5)
+
+void iopin_initialize_bits(iopin_t *, int);
+
 /*
  * IIM
  */
@@ -1116,66 +1139,68 @@ typedef struct fifoc512x {
  *
  * Overall size of FIFOC memory is not documented in the MPC5121e RM, but
  * tests indicate that it is 1024 words total.
+ *
+ * *_TX_SIZE and *_RX_SIZE is the number of 4-byte words for FIFO slice.
  */
-#define FIFOC_PSC0_TX_SIZE     0x0     /* number of 4-byte words for FIFO slice */
+#define FIFOC_PSC0_TX_SIZE     0x04
 #define FIFOC_PSC0_TX_ADDR     0x0
-#define FIFOC_PSC0_RX_SIZE     0x0
-#define FIFOC_PSC0_RX_ADDR     0x0
+#define FIFOC_PSC0_RX_SIZE     0x04
+#define FIFOC_PSC0_RX_ADDR     0x10
 
-#define FIFOC_PSC1_TX_SIZE     0x0
-#define FIFOC_PSC1_TX_ADDR     0x0
-#define FIFOC_PSC1_RX_SIZE     0x0
-#define FIFOC_PSC1_RX_ADDR     0x0
+#define FIFOC_PSC1_TX_SIZE     0x04
+#define FIFOC_PSC1_TX_ADDR     0x20
+#define FIFOC_PSC1_RX_SIZE     0x04
+#define FIFOC_PSC1_RX_ADDR     0x30
 
-#define FIFOC_PSC2_TX_SIZE     0x0
-#define FIFOC_PSC2_TX_ADDR     0x0
-#define FIFOC_PSC2_RX_SIZE     0x0
-#define FIFOC_PSC2_RX_ADDR     0x0
+#define FIFOC_PSC2_TX_SIZE     0x04
+#define FIFOC_PSC2_TX_ADDR     0x40
+#define FIFOC_PSC2_RX_SIZE     0x04
+#define FIFOC_PSC2_RX_ADDR     0x50
 
 #define FIFOC_PSC3_TX_SIZE     0x04
-#define FIFOC_PSC3_TX_ADDR     0x0
+#define FIFOC_PSC3_TX_ADDR     0x60
 #define FIFOC_PSC3_RX_SIZE     0x04
-#define FIFOC_PSC3_RX_ADDR     0x10
-
-#define FIFOC_PSC4_TX_SIZE     0x0
-#define FIFOC_PSC4_TX_ADDR     0x0
-#define FIFOC_PSC4_RX_SIZE     0x0
-#define FIFOC_PSC4_RX_ADDR     0x0
-
-#define FIFOC_PSC5_TX_SIZE     0x0
-#define FIFOC_PSC5_TX_ADDR     0x0
-#define FIFOC_PSC5_RX_SIZE     0x0
-#define FIFOC_PSC5_RX_ADDR     0x0
-
-#define FIFOC_PSC6_TX_SIZE     0x0
-#define FIFOC_PSC6_TX_ADDR     0x0
-#define FIFOC_PSC6_RX_SIZE     0x0
-#define FIFOC_PSC6_RX_ADDR     0x0
-
-#define FIFOC_PSC7_TX_SIZE     0x0
-#define FIFOC_PSC7_TX_ADDR     0x0
-#define FIFOC_PSC7_RX_SIZE     0x0
-#define FIFOC_PSC7_RX_ADDR     0x0
-
-#define FIFOC_PSC8_TX_SIZE     0x0
-#define FIFOC_PSC8_TX_ADDR     0x0
-#define FIFOC_PSC8_RX_SIZE     0x0
-#define FIFOC_PSC8_RX_ADDR     0x0
-
-#define FIFOC_PSC9_TX_SIZE     0x0
-#define FIFOC_PSC9_TX_ADDR     0x0
-#define FIFOC_PSC9_RX_SIZE     0x0
-#define FIFOC_PSC9_RX_ADDR     0x0
-
-#define FIFOC_PSC10_TX_SIZE    0x0
-#define FIFOC_PSC10_TX_ADDR    0x0
-#define FIFOC_PSC10_RX_SIZE    0x0
-#define FIFOC_PSC10_RX_ADDR    0x0
-
-#define FIFOC_PSC11_TX_SIZE    0x0
-#define FIFOC_PSC11_TX_ADDR    0x0
-#define FIFOC_PSC11_RX_SIZE    0x0
-#define FIFOC_PSC11_RX_ADDR    0x0
+#define FIFOC_PSC3_RX_ADDR     0x70
+
+#define FIFOC_PSC4_TX_SIZE     0x04
+#define FIFOC_PSC4_TX_ADDR     0x80
+#define FIFOC_PSC4_RX_SIZE     0x04
+#define FIFOC_PSC4_RX_ADDR     0x90
+
+#define FIFOC_PSC5_TX_SIZE     0x04
+#define FIFOC_PSC5_TX_ADDR     0xa0
+#define FIFOC_PSC5_RX_SIZE     0x04
+#define FIFOC_PSC5_RX_ADDR     0xb0
+
+#define FIFOC_PSC6_TX_SIZE     0x04
+#define FIFOC_PSC6_TX_ADDR     0xc0
+#define FIFOC_PSC6_RX_SIZE     0x04
+#define FIFOC_PSC6_RX_ADDR     0xd0
+
+#define FIFOC_PSC7_TX_SIZE     0x04
+#define FIFOC_PSC7_TX_ADDR     0xe0
+#define FIFOC_PSC7_RX_SIZE     0x04
+#define FIFOC_PSC7_RX_ADDR     0xf0
+
+#define FIFOC_PSC8_TX_SIZE     0x04
+#define FIFOC_PSC8_TX_ADDR     0x100
+#define FIFOC_PSC8_RX_SIZE     0x04
+#define FIFOC_PSC8_RX_ADDR     0x110
+
+#define FIFOC_PSC9_TX_SIZE     0x04
+#define FIFOC_PSC9_TX_ADDR     0x120
+#define FIFOC_PSC9_RX_SIZE     0x04
+#define FIFOC_PSC9_RX_ADDR     0x130
+
+#define FIFOC_PSC10_TX_SIZE    0x04
+#define FIFOC_PSC10_TX_ADDR    0x140
+#define FIFOC_PSC10_RX_SIZE    0x04
+#define FIFOC_PSC10_RX_ADDR    0x150
+
+#define FIFOC_PSC11_TX_SIZE    0x04
+#define FIFOC_PSC11_TX_ADDR    0x160
+#define FIFOC_PSC11_RX_SIZE    0x04
+#define FIFOC_PSC11_RX_ADDR    0x170
 
 /*
  * SATA
@@ -1243,4 +1268,10 @@ static inline u32 get_pata_base (void)
 }
 #endif /* __ASSEMBLY__ */
 
+#define CONFIG_SYS_MPC512x_USB_OFFSET   0x4000
+#define CONFIG_SYS_MPC512x_USB_ADDR \
+                       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET)
+
+#define IIM_BASE_ADDR  (CONFIG_SYS_IMMR + offsetof(immap_t, iim))
+
 #endif /* __IMMAP_512x__ */