Merge remote-tracking branch 'u-boot-samsung/master'

[karo-tx-uboot.git] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 741b8618d11fbd25ffd99e6658b95e122f5e72cf..8258ab3805009cd148dd9607a78f5acd556ddef4 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1748,7 +1748,8 @@ typedef struct ccsr_gur {
 /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT      8
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK    0x3f
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+       defined(CONFIG_PPC_T4080)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xfc000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  26
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL                0x00fe0000
@@ -1848,7 +1849,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII          0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE         0x00180000
 #endif
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+       defined(CONFIG_PPC_T4080)
 #define FSL_CORENET_RCWSR13_EC1                        0x60000000 /* bits 417..418 */
 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII       0x00000000
 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO               0x40000000
@@ -1897,7 +1899,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
        u32     sata2liodnr;    /* SATA 2 LIODN */
        u32     sata3liodnr;    /* SATA 3 LIODN */
        u32     sata4liodnr;    /* SATA 4 LIODN */
-       u8      res22[24];
+       u8      res22[20];
+       u32     tdmliodnr;      /* TDM LIODN */
        u32     qeliodnr;       /* QE LIODN */
        u8      res_57c[4];
        u32     dma1liodnr;     /* DMA 1 LIODN */
@@ -2519,14 +2522,17 @@ typedef struct serdes_corenet {
 #define SRDS_PLLCR0_RFCK_SEL_150       0x30000000
 #define SRDS_PLLCR0_RFCK_SEL_161_13    0x40000000
 #define SRDS_PLLCR0_RFCK_SEL_122_88    0x50000000
+#define SRDS_PLLCR0_PLL_LCK            0x00800000
 #define SRDS_PLLCR0_DCBIAS_OUT_EN      0x02000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK     0x000f0000
 #define SRDS_PLLCR0_FRATE_SEL_5                0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_4_9152   0x00030000
 #define SRDS_PLLCR0_FRATE_SEL_3_75     0x00050000
 #define SRDS_PLLCR0_FRATE_SEL_5_15     0x00060000
 #define SRDS_PLLCR0_FRATE_SEL_4                0x00070000
-#define SRDS_PLLCR0_FRATE_SEL_3_12     0x00090000
-#define SRDS_PLLCR0_FRATE_SEL_3                0x000a0000
+#define SRDS_PLLCR0_FRATE_SEL_3_125    0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3_0      0x000a0000
+#define SRDS_PLLCR0_FRATE_SEL_3_072    0x000c0000
 #define SRDS_PLLCR0_DCBIAS_OVRD                0x000000F0
 #define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT  4
                u32     pllcr1; /* PLL Control Register 1 */
@@ -2861,6 +2867,21 @@ struct ccsr_pman {
        u8      res_f4[0xf0c];
 };
 #endif
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
+struct ccsr_sfp_regs {
+       u32 ospr;               /* 0x200 */
+       u32 reserved0[14];
+       u32 srk_hash[8];        /* 0x23c Super Root Key Hash */
+       u32 oem_uid;            /* 0x9c OEM Unique ID */
+       u8 reserved2[0x04];
+       u32 ovpr;                       /* 0xA4  Intent To Secure */
+       u8 reserved4[0x08];
+       u32 fsl_uid;            /* 0xB0  FSL Unique ID */
+       u8 reserved5[0x04];
+       u32 fsl_spfr0;          /* Scratch Pad Fuse Register 0 */
+       u32 fsl_spfr1;          /* Scratch Pad Fuse Register 1 */
+};
+#endif
 
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET      0x0000
@@ -2874,6 +2895,14 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET         0xA000
 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET      0xE1000
 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET     0xE2000
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
+/* In SFPv3, OSPR register is now at offset 0x200.
+ *  * So directly mapping sfp register map to this address */
+#define CONFIG_SYS_OSPR_OFFSET                  0x200
+#define CONFIG_SYS_SFP_OFFSET            (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
+#else
+#define CONFIG_SYS_SFP_OFFSET                   0xE8000
+#endif
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET   0xEA000
 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET  0xEB000
 #define CONFIG_SYS_FSL_CPC_OFFSET              0x10000
@@ -2887,6 +2916,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_LBC_OFFSET          0x124000
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET          0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET         0x130000
+#define CONFIG_SYS_MPC85xx_TDM_OFFSET          0x185000
 #define CONFIG_SYS_MPC85xx_QE_OFFSET           0x140000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET     0x1e0000
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
@@ -3092,6 +3122,9 @@ struct ccsr_pman {
 #define CONFIG_SYS_PCIE4_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
 
+#define CONFIG_SYS_SFP_ADDR  \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
+
 #define TSEC_BASE_ADDR         (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR         (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)