powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs

[karo-tx-uboot.git] / arch / powerpc / include / asm / ppc405.h

diff --git a/arch/powerpc/include/asm/ppc405.h b/arch/powerpc/include/asm/ppc405.h
index 14a7a379fd1fa093557e4b1983b52466145c1c37..f2ed16a216f69c34a554876e827b199933c9acf4 100644 (file)
--- a/arch/powerpc/include/asm/ppc405.h
+++ b/arch/powerpc/include/asm/ppc405.h
@@ -1,25 +1,6 @@
-/*----------------------------------------------------------------------------+
-|   This source code is dual-licensed.  You may use it under the terms of the
-|   GNU General Public License version 2, or under the license below.
-|
-|      This source code has been made available to you by IBM on an AS-IS
-|      basis.  Anyone receiving this source is licensed under IBM
-|      copyrights to use it in any way he or she deems fit, including
-|      copying it, modifying it, compiling it, and redistributing it either
-|      with or without modifications.  No license under IBM patents or
-|      patent applications is to be implied by the copyright license.
-|
-|      Any user of this software should understand that IBM cannot provide
-|      technical support for this software and will not be responsible for
-|      any consequences resulting from the use of this software.
-|
-|      Any person who transfers this source code or any derivative work
-|      must include the IBM copyright notice, this paragraph, and the
-|      preceding two paragraphs in the transferred software.
-|
-|      COPYRIGHT   I B M   CORPORATION 1999
-|      LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
-+----------------------------------------------------------------------------*/
+/*
+ * SPDX-License-Identifier:    GPL-2.0 IBM-pibs
+ */
 
 #ifndef        __PPC405_H__
 #define __PPC405_H__
@@ -28,11 +9,7 @@
 #define PPC_128MB_SACR_BIT(addr)       ((addr) >> 27)
 #define PPC_128MB_SACR_VALUE(addr)     PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
 
-#ifndef CONFIG_IOP480
 #define CONFIG_SYS_DCACHE_SIZE         (16 << 10)      /* For AMCC 405 CPUs */
-#else
-#define CONFIG_SYS_DCACHE_SIZE         (2 << 10)       /* For PLX IOP480(403)*/
-#endif
 
 /* DCR registers */
 #define PLB0_ACR       0x0087