Coding Style cleanup: remove trailing white space

[karo-tx-uboot.git] / arch / powerpc / include / asm / ppc4xx-sdram.h

diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
index 92be514b40419573095b97ac6156982fe0a96ae9..12d6d038c7b10cd047dad728389b0bf6008f2c6d 100644 (file)
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -2,23 +2,7 @@
  * (C) Copyright 2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _PPC4xx_SDRAM_H_
@@ -63,6 +47,8 @@
 #define SDRAM_CFG0     0x20    /* memory controller options 0          */
 #define SDRAM_CFG1     0x21    /* memory controller options 1          */
 
+#define SDRAM0_BESR0   0x0000  /* bus error status reg 0               */
+#define SDRAM0_BESR1   0x0008  /* bus error status reg 1               */
 #define SDRAM0_BEAR    0x0010  /* bus error address reg                */
 #define SDRAM0_SLIO    0x0018  /* ddr sdram slave interface options    */
 #define SDRAM0_CFG0    0x0020  /* ddr sdram options 0                  */
@@ -290,7 +276,7 @@
  */
 #if defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
+    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
 #define SDRAM_RXBAS_SDBA_MASK          0xFFE00000      /* Base address */
 #define SDRAM_RXBAS_SDBA_ENCODE(n)     ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
 #define SDRAM_RXBAS_SDBA_DECODE(n)     ((((phys_size_t)(n)) & 0xFFE00000) << 2)
@@ -344,6 +330,9 @@
 #define SDRAM_RXBAS_SDSZ_2048          SDRAM_RXBAS_SDSZ_2048MB
 #define SDRAM_RXBAS_SDSZ_4096          SDRAM_RXBAS_SDSZ_4096MB
 #define SDRAM_RXBAS_SDSZ_8192          SDRAM_RXBAS_SDSZ_8192MB
+#endif /* CONFIG_405EX */
+
+/* The mode definitions are the same for all PPC4xx variants */
 #define SDRAM_RXBAS_SDAM_MODE0         PPC_REG_VAL(23, 0x0)
 #define SDRAM_RXBAS_SDAM_MODE1         PPC_REG_VAL(23, 0x1)
 #define SDRAM_RXBAS_SDAM_MODE2         PPC_REG_VAL(23, 0x2)
@@ -356,11 +345,11 @@
 #define SDRAM_RXBAS_SDAM_MODE9         PPC_REG_VAL(23, 0x9)
 #define SDRAM_RXBAS_SDBE_DISABLE       PPC_REG_VAL(31, 0x0)
 #define SDRAM_RXBAS_SDBE_ENABLE                PPC_REG_VAL(31, 0x1)
-#endif /* CONFIG_405EX */
 
 /*
  * Memory controller registers
  */
+#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
 #define SDRAM_BESR     0x00    /* PLB bus error status (read/clear)         */
 #define SDRAM_BESRT    0x01    /* PLB bus error status (test/set)           */
 #define SDRAM_BEARL    0x02    /* PLB bus error address low                 */
@@ -369,11 +358,10 @@
 #define SDRAM_WMIRQT   0x07    /* PLB write master interrupt (test/set)     */
 #define SDRAM_PLBOPT   0x08    /* PLB slave options                         */
 #define SDRAM_PUABA    0x09    /* PLB upper address base                    */
-#ifndef CONFIG_405EX
-#define SDRAM_MCSTAT   0x14    /* memory controller status                  */
-#else
 #define SDRAM_MCSTAT   0x1F    /* memory controller status                  */
-#endif
+#else /* CONFIG_405EX || CONFIG_APM821XX */
+#define SDRAM_MCSTAT   0x14    /* memory controller status                  */
+#endif /* CONFIG_405EX || CONFIG_APM821XX */
 #define SDRAM_MCOPT1   0x20    /* memory controller options 1               */
 #define SDRAM_MCOPT2   0x21    /* memory controller options 2               */
 #define SDRAM_MODT0    0x22    /* on die termination for bank 0             */
@@ -419,12 +407,12 @@
 #define SDRAM_MEMODE   0x89    /* memory extended mode                      */
 #define SDRAM_ECCES    0x98    /* ECC error status                          */
 #define SDRAM_CID      0xA4    /* core ID                                   */
-#ifndef CONFIG_405EX
+#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX)
 #define SDRAM_RID      0xA8    /* revision ID                               */
 #endif
 #define SDRAM_FCSR     0xB0    /* feedback calibration status               */
 #define SDRAM_RTSR     0xB1    /* run time status tracking                  */
-#ifdef CONFIG_405EX
+#if  defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
 #define SDRAM_RID      0xF8    /* revision ID                               */
 #endif
 
@@ -947,8 +935,6 @@
 #define SDRAM_RTSR_TRK1SM_ATPLS1       0x80000000      /* atpls1 state         */
 #define SDRAM_RTSR_TRK1SM_RESET                0xC0000000      /* reset  state         */
 
-#define SDR0_MFR_FIXD                  0x10000000      /* Workaround for PCI/DMA */
-
 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */
 
 #if defined(CONFIG_SDRAM_PPC4xx_DENALI_DDR2)
@@ -1394,10 +1380,15 @@
 #endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
 
 #ifndef __ASSEMBLY__
+struct sdram_timing {
+       u32 wrdtr;
+       u32 clktr;
+};
+
 /*
  * Prototypes
  */
-inline void ppc4xx_ibm_ddr2_register_dump(void);
+void ppc4xx_ibm_ddr2_register_dump(void);
 u32 mfdcr_any(u32);
 void mtdcr_any(u32, u32);
 u32 ddr_wrdtr(u32);