Merge remote-tracking branch 'u-boot/master' into test

[karo-tx-uboot.git] / arch / powerpc / include / asm / processor.h

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 8c91f0849b86899c860d1d08b1640183f677d8b4..a6f121e113a617f75a65dd683a5aae18f848d2ad 100644 (file)
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -7,8 +7,6 @@
  */
 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
 
-#include <linux/config.h>
-
 #include <asm/ptrace.h>
 #include <asm/types.h>
 
@@ -507,6 +505,15 @@
 #define   L2CSR0_L2IO          0x00100000      /* L2 Cache Instruction Only */
 #define   L2CSR0_L2DO          0x00010000      /* L2 Cache Data Only */
 #define   L2CSR0_L2REP         0x00003000      /* L2 Line Replacement Algo */
+
+/* e6500 */
+#define   L2CSR0_L2REP_SPLRUAGE        0x00000000      /* L2REP Streaming PLRU with Aging */
+#define   L2CSR0_L2REP_FIFO    0x00001000      /* L2REP FIFO */
+#define   L2CSR0_L2REP_SPLRU   0x00002000      /* L2REP Streaming PLRU */
+#define   L2CSR0_L2REP_PLRU    0x00003000      /* L2REP PLRU */
+
+#define   L2CSR0_L2REP_MODE    L2CSR0_L2REP_SPLRUAGE
+
 #define   L2CSR0_L2FL          0x00000800      /* L2 Cache Flush */
 #define   L2CSR0_L2LFC         0x00000400      /* L2 Cache Lock Flash Clear */
 #define   L2CSR0_L2LOA         0x00000080      /* L2 Cache Lock Overflow Allocate */
@@ -575,6 +582,16 @@
 #define SPRN_MSSSR0    0x3f7
 #endif
 
+#define SPRN_HDBCR0    0x3d0
+#define SPRN_HDBCR1    0x3d1
+#define SPRN_HDBCR2    0x3d2
+#define SPRN_HDBCR3    0x3d3
+#define SPRN_HDBCR4    0x3d4
+#define SPRN_HDBCR5    0x3d5
+#define SPRN_HDBCR6    0x3d6
+#define SPRN_HDBCR7    0x277
+#define SPRN_HDBCR8    0x278
+
 /* Short-hand versions for a number of the above SPRNs */
 
 #define CTR    SPRN_CTR        /* Counter Register */
@@ -828,7 +845,7 @@
 /* System-On-Chip Version Register (SVR) field extraction */
 
 #define SVR_VER(svr)   (((svr) >> 16) & 0xFFFF) /* Version field */
-#define SVR_REV(svr)   (((svr) >>  0) & 0xFFFF) /* Revision field */
+#define SVR_REV(svr)   (((svr) >>  0) & 0xFF)   /* Revision field */
 
 #define SVR_CID(svr)   (((svr) >> 28) & 0x0F)   /* Company or manufacturer ID */
 #define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F)   /* SOC integration options */
@@ -875,9 +892,6 @@
 #define PVR_405GP_RC   0x40110082
 #define PVR_405GP_RD   0x401100C4
 #define PVR_405GP_RE   0x40110145  /* same as pc405cr rev c */
-#define PVR_405CR_RA   0x40110041
-#define PVR_405CR_RB   0x401100C5
-#define PVR_405CR_RC   0x40110145  /* same as pc405gp rev e */
 #define PVR_405EP_RA   0x51210950
 #define PVR_405GPR_RB  0x50910951
 #define PVR_405EZ_RA   0x41511460
@@ -1024,9 +1038,6 @@
 
 /* System Version Register (SVR) field extraction */
 
-#define SVR_VER(svr)   (((svr) >>  16) & 0xFFFF)       /* Version field */
-#define SVR_REV(svr)   (((svr) >>   0) & 0xFFFF)       /* Revison field */
-
 #define SVR_SUBVER(svr)        (((svr) >>  8) & 0xFF)  /* Process/MFG sub-version */
 
 #define SVR_FAM(svr)   (((svr) >> 20) & 0xFFF) /* Family field */
@@ -1099,6 +1110,11 @@
 #define SVR_P5040      0x820400
 #define SVR_T4240      0x824000
 #define SVR_T4120      0x824001
+#define SVR_T4160      0x824100
+#define SVR_T4080      0x824102
+#define SVR_C291       0x850000
+#define SVR_C292       0x850020
+#define SVR_C293       0x850030
 #define SVR_B4860      0X868000
 #define SVR_G4860      0x868001
 #define SVR_G4060      0x868003
@@ -1106,6 +1122,14 @@
 #define SVR_G4440      0x868101
 #define SVR_B4420      0x868102
 #define SVR_B4220      0x868103
+#define SVR_T1040      0x852000
+#define SVR_T1041      0x852001
+#define SVR_T1042      0x852002
+#define SVR_T1020      0x852100
+#define SVR_T1021      0x852101
+#define SVR_T1022      0x852102
+#define SVR_T2080      0x853000
+#define SVR_T2081      0x853100
 
 #define SVR_8610       0x80A000
 #define SVR_8641       0x809000
@@ -1174,6 +1198,8 @@ struct cpu_type {
 struct cpu_type *identify_cpu(u32 ver);
 int fixup_cpu(void);
 
+int fsl_qoriq_core_to_cluster(unsigned int core);
+
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 #define CPU_TYPE_ENTRY(n, v, nc) \
        { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \
@@ -1331,7 +1357,7 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 #elif defined(CONFIG_GEMINI)
 #define _machine _MACH_gemini
 #define have_of 0
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 #define _machine _MACH_8260
 #define have_of 0
 #elif defined(CONFIG_SANDPOINT)