x86: Add support for MTRRs

[karo-tx-uboot.git] / arch / x86 / cpu / coreboot / coreboot.c

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index cfacc05875496f1243555f3671299089bc48d1e2..6d06d5af19e5f7f38ce19676f97a0ac25d1803cc 100644 (file)
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -15,6 +15,7 @@
 #include <asm/cache.h>
 #include <asm/cpu.h>
 #include <asm/io.h>
+#include <asm/mtrr.h>
 #include <asm/arch/tables.h>
 #include <asm/arch/sysinfo.h>
 #include <asm/arch/timestamp.h>
@@ -64,11 +65,6 @@ int board_eth_init(bd_t *bis)
        return pci_eth_init(bis);
 }
 
-#define MTRR_TYPE_WP          5
-#define MTRRcap_MSR           0xfe
-#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
-#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
-
 void board_final_cleanup(void)
 {
        /* Un-cache the ROM so the kernel has one
@@ -77,15 +73,17 @@ void board_final_cleanup(void)
         * Coreboot should have assigned this to the
         * top available variable MTRR.
         */
-       u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1;
-       u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff;
+       u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1;
+       u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff;
 
        /* Make sure this MTRR is the correct Write-Protected type */
-       if (top_type == MTRR_TYPE_WP) {
-               disable_caches();
-               wrmsrl(MTRRphysBase_MSR(top_mtrr), 0);
-               wrmsrl(MTRRphysMask_MSR(top_mtrr), 0);
-               enable_caches();
+       if (top_type == MTRR_TYPE_WRPROT) {
+               struct mtrr_state state;
+
+               mtrr_open(&state);
+               wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
+               wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
+               mtrr_close(&state);
        }
 
        /* Issue SMI to Coreboot to lock down ME and registers */