x86: coreboot: Implement recursively scanning PCI busses

[karo-tx-uboot.git] / arch / x86 / cpu / coreboot / pci.c

diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 0ddc97501b7807ef72c322d0e88ab5e2bf4b9846..8f941674806ce749087a0d678abfe2aa3c131dd4 100644 (file)
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -31,15 +31,35 @@
 
 static struct pci_controller coreboot_hose;
 
+static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
+                             struct pci_config_table *table)
+{
+       u8 secondary;
+       hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
+       hose->last_busno = max(hose->last_busno, secondary);
+       pci_hose_scan_bus(hose, secondary);
+}
+
+static struct pci_config_table pci_coreboot_config_table[] = {
+       /* vendor, device, class, bus, dev, func */
+       { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
+               PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
+       {}
+};
+
 void pci_init_board(void)
 {
+       coreboot_hose.config_table = pci_coreboot_config_table;
        coreboot_hose.first_busno = 0;
-       coreboot_hose.last_busno = 0xff;
-       coreboot_hose.region_count = 0;
+       coreboot_hose.last_busno = 0;
+
+       pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
+               PCI_REGION_MEM);
+       coreboot_hose.region_count = 1;
 
        pci_setup_type1(&coreboot_hose);
 
        pci_register_hose(&coreboot_hose);
 
-       coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose);
+       pci_hose_scan(&coreboot_hose);
 }