ppc4xx: Remove 4xx NAND booting support

[karo-tx-uboot.git] / board / amcc / sequoia / init.S

diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index b31e9db3f9102b34906d2d3c4b408128871b82b8..f876639d353fdca8c36b6fc0d17c165749d29783 100644 (file)
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -48,11 +48,7 @@ tlbtab:
        /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
         * speed up boot process. It is patched after relocation to enable SA_I
         */
-#ifndef CONFIG_NAND_SPL
        tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
-#else
-       tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
-#endif
 
 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
@@ -81,31 +77,3 @@ tlbtab:
        tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
 
        tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-       /*
-        * For NAND booting the first TLB has to be reconfigured to full size
-        * and with caching disabled after running from RAM!
-        */
-#define TLB00  TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01  TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02  TLB2(AC_RWX | SA_IG)
-
-       .globl  reconfig_tlb0
-reconfig_tlb0:
-       sync
-       isync
-       addi    r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */
-       lis     r5,TLB00@h
-       ori     r5,r5,TLB00@l
-       tlbwe   r5,r4,0x0000            /* Save it out */
-       lis     r5,TLB01@h
-       ori     r5,r5,TLB01@l
-       tlbwe   r5,r4,0x0001            /* Save it out */
-       lis     r5,TLB02@h
-       ori     r5,r5,TLB02@l
-       tlbwe   r5,r4,0x0002            /* Save it out */
-       sync
-       isync
-       blr
-#endif