* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
* Keith Outwater, keith_outwater@mvis.com.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier: GPL-2.0+
*/
/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */
}
/* Set the FPGA's PROG_B line to the specified level */
-int xilinx_pgm_fn(int assert, int flush, int cookie)
+int xilinx_pgm_config_fn(int assert, int flush, int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
* asserted (low).
*/
-int xilinx_init_fn(int cookie)
+int xilinx_init_config_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
}
/* Test the state of the active-high FPGA DONE pin */
-int xilinx_done_fn(int cookie)
+int xilinx_done_config_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
}
/* Abort an FPGA operation */
-int xilinx_abort_fn(int cookie)
+int xilinx_abort_config_fn(int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
/* ensure all SPI peripherals and FPGAs are deselected */
return rc;
}
-int xilinx_clk_fn(int assert_clk, int flush, int cookie)
+int xilinx_clk_config_fn(int assert_clk, int flush, int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
return assert_clk;
}
-int xilinx_wr_fn(int assert_write, int flush, int cookie)
+int xilinx_wr_config_fn(int assert_write, int flush, int cookie)
{
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
return assert_write;
}
-int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie)
+int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
{
size_t bytecount = 0;
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
* relocated at runtime.
* FIXME: relocation not yet working for coldfire, see below!
*/
-Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = {
+xilinx_spartan3_slave_serial_fns xilinx_fns = {
xilinx_pre_config_fn,
- xilinx_pgm_fn,
- xilinx_clk_fn,
- xilinx_init_fn,
- xilinx_done_fn,
- xilinx_wr_fn,
+ xilinx_pgm_config_fn,
+ xilinx_clk_config_fn,
+ xilinx_init_config_fn,
+ xilinx_done_config_fn,
+ xilinx_wr_config_fn,
0,
- xilinx_fastwr_fn
+ xilinx_fastwr_config_fn
};
-Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
- {Xilinx_Spartan3,
+xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
+ {xilinx_spartan3,
slave_serial,
XILINX_XC3S4000_SIZE,
(void *)&xilinx_fns,
- 0}
+ 0,
+ &spartan3_op}
};
/* Initialize the fpga. Return 1 on success, 0 on failure. */
* so set stuff here instead of static initialisation:
*/
xilinx_fns.pre = xilinx_pre_config_fn;
- xilinx_fns.pgm = xilinx_pgm_fn;
- xilinx_fns.clk = xilinx_clk_fn;
- xilinx_fns.init = xilinx_init_fn;
- xilinx_fns.done = xilinx_done_fn;
- xilinx_fns.wr = xilinx_wr_fn;
- xilinx_fns.bwr = xilinx_fastwr_fn;
+ xilinx_fns.pgm = xilinx_pgm_config_fn;
+ xilinx_fns.clk = xilinx_clk_config_fn;
+ xilinx_fns.init = xilinx_init_config_fn;
+ xilinx_fns.done = xilinx_done_config_fn;
+ xilinx_fns.wr = xilinx_wr_config_fn;
+ xilinx_fns.bwr = xilinx_fastwr_config_fn;
xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
fpga_add(fpga_xilinx, &xilinx_fpga[i]);
}