Merge branch 'master' of git://git.denx.de/u-boot-samsung

[karo-tx-uboot.git] / board / cray / L1 / L1.c

diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c
index 8a06ecc66504e91f4aa4b8b3577c826e62a9b3b2..d87b6ef90633b274384e04c34ed1ae120959001c 100644 (file)
--- a/board/cray/L1/L1.c
+++ b/board/cray/L1/L1.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
-#include <4xx_i2c.h>
+#include <asm/ppc4xx-i2c.h>
 #include <command.h>
 #include <rtc.h>
 #include <post.h>
@@ -113,13 +113,13 @@ int board_early_init_f (void)
 {
        /* Running from ROM: global data is still READONLY */
        init_sdram ();
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
-       mtdcr (uiccr, 0x00000020);      /* set all but FPGA SMI to be non-critical */
-       mtdcr (uicpr, 0xFFFFFFE0);      /* set int polarities */
-       mtdcr (uictr, 0x10000000);      /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);     /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
+       mtdcr (UIC0CR, 0x00000020);     /* set all but FPGA SMI to be non-critical */
+       mtdcr (UIC0PR, 0xFFFFFFE0);     /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
        return 0;
 }
 
@@ -169,12 +169,6 @@ int misc_init_r (void)
        return (0);
 }
 
-/* ------------------------------------------------------------------------- */
-phys_size_t initdram (int board_type)
-{
-       return (L1_MEMSIZE);
-}
-
 /* ------------------------------------------------------------------------- */
 /* stubs so we can print dates w/o any nvram RTC.*/
 int rtc_get (struct rtc_time *tmp)
@@ -198,8 +192,8 @@ static void init_sdram (void)
  unsigned long tmp;
 
        /* write SDRAM bank 0 register */
-       mtdcr (memcfga, mem_mb0cf);
-       mtdcr (memcfgd, 0x00062001);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+       mtdcr (SDRAM0_CFGDATA, 0x00062001);
 
 /* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.     */
 /* To set the appropriate timings, we need to know the SDRAM speed.    */
@@ -212,26 +206,26 @@ static void init_sdram (void)
        /* divisor = ((mfdcr(strap)>> 28) & 0x3); */
 
 /* write SDRAM timing for 100MHz. */
-       mtdcr (memcfga, mem_sdtr1);
-       mtdcr (memcfgd, 0x0086400D);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+       mtdcr (SDRAM0_CFGDATA, 0x0086400D);
 
 /* write SDRAM refresh interval register */
-       mtdcr (memcfga, mem_rtr);
-       mtdcr (memcfgd, 0x05F00000);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+       mtdcr (SDRAM0_CFGDATA, 0x05F00000);
        udelay (200);
 
 /* sdram controller.*/
-       mtdcr (memcfga, mem_mcopt1);
-       mtdcr (memcfgd, 0x90800000);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+       mtdcr (SDRAM0_CFGDATA, 0x90800000);
        udelay (200);
 
 /* initially, disable ECC on all banks */
        udelay (200);
-       mtdcr (memcfga, mem_ecccf);
-       tmp = mfdcr (memcfgd);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+       tmp = mfdcr (SDRAM0_CFGDATA);
        tmp &= 0xff0fffff;
-       mtdcr (memcfga, mem_ecccf);
-       mtdcr (memcfgd, tmp);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+       mtdcr (SDRAM0_CFGDATA, tmp);
 
        return;
 }
@@ -245,7 +239,7 @@ int testdram (void)
        uint *pend = (uint *) L1_MEMSIZE;
        uint *p;
 
-       if (getenv_r("booted",NULL,0) <= 0)
+       if (getenv_f("booted",NULL,0) <= 0)
        {
                printf ("testdram..");
        /*AA*/
@@ -282,18 +276,18 @@ int testdram (void)
        }
        printf ("Enable ECC..");
 
-       mtdcr (memcfga, mem_mcopt1);
-       tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
-       mtdcr (memcfga, mem_mcopt1);
-       mtdcr (memcfgd, tmp);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+       tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+       mtdcr (SDRAM0_CFGDATA, tmp);
        udelay (600);
        for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L)
                ;
        udelay (400);
-       mtdcr (memcfga, mem_ecccf);
-       tmp = mfdcr (memcfgd);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+       tmp = mfdcr (SDRAM0_CFGDATA);
        tmp |= 0x00800000;
-       mtdcr (memcfgd, tmp);
+       mtdcr (SDRAM0_CFGDATA, tmp);
        udelay (400);
        printf ("enabled.\n");
        return (0);