#include <common.h>
#include <asm/processor.h>
-#include <405gp_i2c.h>
+#include <asm/ppc4xx-i2c.h>
#include <command.h>
-#include <cmd_nvedit.h>
-#include <cmd_bootm.h>
#include <rtc.h>
+#include <post.h>
#include <net.h>
#include <malloc.h>
* space.
* on the server this looks like:
*
- * option space U-Boot;
- * option U-Boot.initrd code 3 = string;
- * option U-Boot.bootcmd code 4 = string;
- * option U-Boot.bootflags code 5 = string;
- * option U-Boot.rootdev code 6 = string;
+ * option space CRAYL1;
+ * option CRAYL1.initrd code 3 = string;
+ * ..etc...
*/
#define DHCP_VENDOR_SPECX 43
#define DHCP_VX_INITRD 3
#define DHCP_VX_BOOTCMD 4
-#define DHCP_VX_BOOTFLAGS 5
+#define DHCP_VX_BOOTARGS 5
#define DHCP_VX_ROOTDEV 6
+#define DHCP_VX_FROMFLASH 7
+#define DHCP_VX_BOOTSCRIPT 8
+#define DHCP_VX_RCFILE 9
+#define DHCP_VX_MAGIC 10
/* Things DHCP server can tellme about. If there's no flash address, then
* they dont participate in 'update' to flash, and we force their values
/* and the other way.. */
{DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"},
{DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"},
- {DHCP_VENDOR_SPECX, DHCP_VX_BOOTFLAGS, NULL, NULL},
+ {DHCP_VENDOR_SPECX, DHCP_VX_FROMFLASH, NULL, "fromflash"},
+ {DHCP_VENDOR_SPECX, DHCP_VX_BOOTSCRIPT, NULL, "bootscript"},
+ {DHCP_VENDOR_SPECX, DHCP_VX_RCFILE, NULL, "rcfile"},
+ {DHCP_VENDOR_SPECX, DHCP_VX_BOOTARGS, NULL, "xbootargs"},
{DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL},
+ {DHCP_VENDOR_SPECX, DHCP_VX_MAGIC, NULL, NULL}
};
#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t)))
-static void init_ecc_sdram (void);
+extern char bootscript[];
+
+/* Here is the boot logic as HUSH script. Overridden by any TFP provided
+ * bootscript file.
+ */
+
+static void init_sdram (void);
/* ------------------------------------------------------------------------- */
-int board_pre_init (void)
+int board_early_init_f (void)
{
- init_ecc_sdram ();
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr (uicer, 0x00000000); /* disable all ints */
- mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
- mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */
- mtdcr (uictr, 0x10000000); /* set int trigger levels */
- mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
+ /* Running from ROM: global data is still READONLY */
+ init_sdram ();
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
+ mtdcr (UIC0PR, 0xFFFFFFE0); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}
{
return (0);
}
+/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
int misc_init_r (void)
{
- unsigned char *s, *e;
+ char *s, *e;
image_header_t *hdr;
time_t timestamp;
struct rtc_time tm;
+ char bootcmd[32];
- hdr = (image_header_t *) (CFG_MONITOR_BASE - sizeof (image_header_t));
- timestamp = (time_t) hdr->ih_time;
+ hdr = (image_header_t *) (CONFIG_SYS_MONITOR_BASE - image_get_header_size ());
+#if defined(CONFIG_FIT)
+ if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+ puts ("Non legacy image format not supported\n");
+ return -1;
+ }
+#endif
+
+ timestamp = (time_t)image_get_time (hdr);
to_tm (timestamp, &tm);
printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
#define FACTORY_SETTINGS 0xFFFC0000
if ((s = getenv ("ethaddr")) == NULL) {
- e = (unsigned char *) (FACTORY_SETTINGS);
+ e = (char *) (FACTORY_SETTINGS);
if (*(e + 0) != '0'
|| *(e + 1) != '0'
|| *(e + 2) != ':'
setenv ("ethaddr", e);
}
}
+ sprintf (bootcmd,"source %X",(unsigned)bootscript);
+ setenv ("bootcmd", bootcmd);
return (0);
}
-/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
-{
- return (L1_MEMSIZE);
-}
-
/* ------------------------------------------------------------------------- */
/* stubs so we can print dates w/o any nvram RTC.*/
-void rtc_get (struct rtc_time *tmp)
+int rtc_get (struct rtc_time *tmp)
{
- return;
+ return 0;
}
-void rtc_set (struct rtc_time *tmp)
+int rtc_set (struct rtc_time *tmp)
{
- return;
+ return 0;
}
void rtc_reset (void)
{
}
/* ------------------------------------------------------------------------- */
-/* Do sdram bank init in C so I can read it..
+/* Do sdram bank init in C so I can read it..no console to print to yet!
*/
-static void init_ecc_sdram (void)
+static void init_sdram (void)
{
- unsigned long tmp, *p;
+ unsigned long tmp;
/* write SDRAM bank 0 register */
- mtdcr (memcfga, mem_mb0cf);
- mtdcr (memcfgd, 0x00062001);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+ mtdcr (SDRAM0_CFGDATA, 0x00062001);
/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
/* To set the appropriate timings, we need to know the SDRAM speed. */
/* We can use the PLB speed since the SDRAM speed is the same as */
/* the PLB speed. The PLB speed is the FBK divider times the */
-/* 405GP reference clock, which on the L1 is 25Mhz. */
-/* Thus, if FBK div is 2, SDRAM is 50Mhz; if FBK div is 3, SDRAM is */
-/* 150Mhz; if FBK is 3, SDRAM is 150Mhz. */
+/* 405GP reference clock, which on the L1 is 25MHz. */
+/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is */
+/* 150MHz; if FBK is 3, SDRAM is 150MHz. */
/* divisor = ((mfdcr(strap)>> 28) & 0x3); */
-/* write SDRAM timing for 100Mhz. */
- mtdcr (memcfga, mem_sdtr1);
- mtdcr (memcfgd, 0x0086400D);
+/* write SDRAM timing for 100MHz. */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+ mtdcr (SDRAM0_CFGDATA, 0x0086400D);
/* write SDRAM refresh interval register */
- mtdcr (memcfga, mem_rtr);
- mtdcr (memcfgd, 0x05F00000);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+ mtdcr (SDRAM0_CFGDATA, 0x05F00000);
udelay (200);
/* sdram controller.*/
- mtdcr (memcfga, mem_mcopt1);
- mtdcr (memcfgd, 0x90800000);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ mtdcr (SDRAM0_CFGDATA, 0x90800000);
udelay (200);
-/* disable ECC on all banks */
- mtdcr (memcfga, mem_ecccf);
- tmp = mfdcr (memcfgd);
+/* initially, disable ECC on all banks */
+ udelay (200);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+ tmp = mfdcr (SDRAM0_CFGDATA);
tmp &= 0xff0fffff;
- mtdcr (memcfga, mem_ecccf);
- mtdcr (memcfgd, tmp);
-
-/* set up SDRAM Controller with ECC enabled */
- mtdcr (memcfga, mem_mcopt1);
- tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
- mtdcr (memcfga, mem_mcopt1);
- mtdcr (memcfgd, tmp);
- udelay (600);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+ mtdcr (SDRAM0_CFGDATA, tmp);
-/* fill all the memory */
- for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE);
- *p++ = 0L);
- udelay (400);
- mtdcr (memcfga, mem_ecccf);
- tmp = mfdcr (memcfgd);
+ return;
+}
+
+extern int memory_post_test (int flags);
+
+int testdram (void)
+{
+ unsigned long tmp;
+ uint *pstart = (uint *) 0x00000000;
+ uint *pend = (uint *) L1_MEMSIZE;
+ uint *p;
+
+ if (getenv_f("booted",NULL,0) <= 0)
+ {
+ printf ("testdram..");
+ /*AA*/
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
+ (uint) p, *p, 0xaaaaaaaa);
+ return 1;
+ }
+ }
+ /*55*/
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
+ (uint) p, *p, 0x55555555);
+ return 1;
+ }
+ }
+ /*addr*/
+ for (p = pstart; p < pend; p++)
+ *p = (unsigned)p;
+ for (p = pstart; p < pend; p++) {
+ if (*p != (unsigned)p) {
+ printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
+ (uint) p, *p, (uint)p);
+ return 1;
+ }
+ }
+ printf ("Success. ");
+ }
+ printf ("Enable ECC..");
-/* enable ECC on bank 0 */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ mtdcr (SDRAM0_CFGDATA, tmp);
+ udelay (600);
+ for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L)
+ ;
+ udelay (400);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+ tmp = mfdcr (SDRAM0_CFGDATA);
tmp |= 0x00800000;
- mtdcr (memcfgd, tmp);
+ mtdcr (SDRAM0_CFGDATA, tmp);
udelay (400);
-
- return;
+ printf ("enabled.\n");
+ return (0);
}
/* ------------------------------------------------------------------------- */
/* set env. */
if (Things[thing].envname)
+ {
setenv (Things[thing].envname, Things[thing].dhcpvalue);
- return (Things[thing].dhcpvalue);
+ }
+ return ((u8 *)(Things[thing].dhcpvalue));
}
/* ------------------------------------------------------------------------- */
oplen -= sub_oplen, sub_op += (sub_oplen + 2)) {
for (thing = 0; thing < N_THINGS; thing++) {
if (*sub_op == Things[thing].dhcp_vendor_option) {
- if (!(retval = dhcp_env_update (thing, sub_op))) {
- return NULL;
- }
+ if (!(retval = dhcp_env_update (thing, sub_op))) {
+ return NULL;
+ }
}
}
}
return NULL;
}
}
- return (thing >= N_THINGS ? NULL : pop);
+ return (pop);
}
projects / karo-tx-uboot.git / blobdiff