Merge 'u-boot-microblaze/zynq' into (u-boot-arm/master'

[karo-tx-uboot.git] / board / csb272 / init.S

diff --git a/board/csb272/init.S b/board/csb272/init.S
index 15b26f8bf86702fcad3ff9b07f2ca401086092ed..b1283aa69a72b129151a1fb2ca08a5d8505f044e 100644 (file)
--- a/board/csb272/init.S
+++ b/board/csb272/init.S
@@ -1,28 +1,8 @@
-/******************************************************************************
- *   This source code is dual-licensed.  You may use it under the terms of the
- *   GNU General Public License version 2, or under the license below.
- *
- *      This source code has been made available to you by IBM on an AS-IS
- *      basis.  Anyone receiving this source is licensed under IBM
- *      copyrights to use it in any way he or she deems fit, including
- *      copying it, modifying it, compiling it, and redistributing it either
- *      with or without modifications.  No license under IBM patents or
- *      patent applications is to be implied by the copyright license.
- *
- *      Any user of this software should understand that IBM cannot provide
- *      technical support for this software and will not be responsible for
- *      any consequences resulting from the use of this software.
- *
- *      Any person who transfers this source code or any derivative work
- *      must include the IBM copyright notice, this paragraph, and the
- *      preceding two paragraphs in the transferred software.
- *
- *      COPYRIGHT   I B M   CORPORATION 1995
- *      LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
- *
- *****************************************************************************/
+/*
+ * SPDX-License-Identifier:    GPL-2.0 ibm-pibs
+ */
 #include <config.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 
 #define _LINUX_CONFIG_H 1      /* avoid reading Linux autoconf.h file  */
 
@@ -175,26 +155,26 @@ sdram_init:
         * Disable memory controller to allow
         * values to be changed.
         */
-       WDCR_SDRAM(mem_mcopt1, 0x00000000)
+       WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
 
        /*
         * Configure Memory Banks
         */
-       WDCR_SDRAM(mem_mb0cf, 0x00084001)
-       WDCR_SDRAM(mem_mb1cf, 0x00000000)
-       WDCR_SDRAM(mem_mb2cf, 0x00000000)
-       WDCR_SDRAM(mem_mb3cf, 0x00000000)
+       WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
+       WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
+       WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
+       WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
 
        /*
         * Set up SDTR1 (SDRAM Timing Register)
         */
-       WDCR_SDRAM(mem_sdtr1, 0x00854009)
+       WDCR_SDRAM(SDRAM0_TR, 0x00854009)
 
        /*
         * Set RTR (Refresh Timing Register)
         */
-       WDCR_SDRAM(mem_rtr,   0x10000000)
-       /* WDCR_SDRAM(mem_rtr,   0x05f00000) */
+       WDCR_SDRAM(SDRAM0_RTR,   0x10000000)
+       /* WDCR_SDRAM(SDRAM0_RTR,   0x05f00000) */
 
        /********************************************************************
         * Delay to ensure 200usec have elapsed since reset. Assume worst
@@ -210,7 +190,7 @@ sdram_init:
        /********************************************************************
         * Set memory controller options reg, MCOPT1.
         *******************************************************************/
-       WDCR_SDRAM(mem_mcopt1,0x80800000)
+       WDCR_SDRAM(SDRAM0_CFG,0x80800000)
 
 ..sdri_done:
        blr                             /* Return to calling function */