Merge branch 'master' of git://git.denx.de/u-boot-arm

[karo-tx-uboot.git] / board / davedenx / qong / qong.c

diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
index b801150036ff393e68e0e2b27bb49a9ef26348a4..781333b8ceb93e41c63a33a0af1c719edca2f826 100644 (file)
--- a/board/davedenx/qong/qong.c
+++ b/board/davedenx/qong/qong.c
@@ -25,6 +25,8 @@
 #include <netdev.h>
 #include <asm/arch/mx31.h>
 #include <asm/arch/mx31-regs.h>
+#include <nand.h>
+#include <fsl_pmic.h>
 #include "qong_fpga.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -38,6 +40,15 @@ int dram_init (void)
        return 0;
 }
 
+static void qong_fpga_reset(void)
+{
+       mx31_gpio_set(QONG_FPGA_RST_PIN, 0);
+       udelay(30);
+       mx31_gpio_set(QONG_FPGA_RST_PIN, 1);
+
+       udelay(300);
+}
+
 int board_init (void)
 {
        /* Chip selects */
@@ -101,6 +112,15 @@ int board_init (void)
        mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
        mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
        mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
+
+       /* FPGA reset  Pin */
+       /* rstn = 0 */
+       mx31_gpio_set(QONG_FPGA_RST_PIN, 0);
+       mx31_gpio_direction(QONG_FPGA_RST_PIN, MX31_GPIO_DIRECTION_OUT);
+
+       /* set interrupt pin as input */
+       mx31_gpio_direction(QONG_FPGA_IRQ_PIN, MX31_GPIO_DIRECTION_IN);
+
 #endif
 
        /* setup pins for UART1 */
@@ -109,6 +129,13 @@ int board_init (void)
        mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
        mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 
+       /* setup pins for SPI (pmic) */
+       mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+       mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+       mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+       mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+       mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+
        /* board id for linux */
        gd->bd->bi_arch_number = MACH_TYPE_QONG;
        gd->bd->bi_boot_params = (0x80000100);  /* adress of boot parameters */
@@ -116,9 +143,21 @@ int board_init (void)
        return 0;
 }
 
+int board_late_init(void)
+{
+       u32 val;
+
+       /* Enable RTC battery */
+       val = pmic_reg_read(REG_POWER_CTL0);
+       pmic_reg_write(REG_POWER_CTL0, val | COINCHEN);
+       pmic_reg_write(REG_INT_STATUS1, RTCRSTI);
+
+       return 0;
+}
+
 int checkboard (void)
 {
-       printf("Board: DAVE/DENX QongEVB-LITE\n");
+       printf("Board: DAVE/DENX Qong\n");
        return 0;
 }
 
@@ -127,32 +166,11 @@ int misc_init_r (void)
 #ifdef CONFIG_QONG_FPGA
        u32 tmp;
 
-       /* FPGA reset */
-       /* rstn = 0 */
-       tmp = __REG(GPIO2_BASE + GPIO_DR);
-       tmp &= (~(1 << QONG_FPGA_RST_PIN));
-       __REG(GPIO2_BASE + GPIO_DR) = tmp;
-       /* set the GPIO as output */
-       tmp = __REG(GPIO2_BASE + GPIO_GDIR);
-       tmp |= (1 << QONG_FPGA_RST_PIN);
-       __REG(GPIO2_BASE + GPIO_GDIR) = tmp;
-       /* wait */
-       udelay(30);
-       /* rstn = 1 */
-       tmp = __REG(GPIO2_BASE + GPIO_DR);
-       tmp |= (1 << QONG_FPGA_RST_PIN);
-       __REG(GPIO2_BASE + GPIO_DR) = tmp;
-       /* set interrupt pin as input */
-       __REG(GPIO2_BASE + GPIO_GDIR) = tmp | (1 << QONG_FPGA_IRQ_PIN);
-       /* wait while the FPGA starts */
-       udelay(300);
-
        tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
        printf("FPGA:  ");
        printf("version register = %u.%u.%u\n",
                (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
 #endif
-
        return 0;
 }
 
@@ -164,3 +182,56 @@ int board_eth_init(bd_t *bis)
        return 0;
 #endif
 }
+
+#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
+static void board_nand_setup(void)
+{
+
+       /* CS3: NAND 8-bit */
+       __REG(CSCR_U(3)) = 0x00004f00;
+       __REG(CSCR_L(3)) = 0x20013b31;
+       __REG(CSCR_A(3)) = 0x00020800;
+       __REG(IOMUXC_GPR) |= 1 << 13;
+
+       mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
+       mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
+       mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
+
+       /* Make sure to reset the fpga else you cannot access NAND */
+       qong_fpga_reset();
+
+       /* Enable NAND flash */
+       mx31_gpio_set(15, 1);
+       mx31_gpio_set(14, 1);
+       mx31_gpio_direction(15, MX31_GPIO_DIRECTION_OUT);
+       mx31_gpio_direction(16, MX31_GPIO_DIRECTION_IN);
+       mx31_gpio_direction(14, MX31_GPIO_DIRECTION_IN);
+       mx31_gpio_set(15, 0);
+
+}
+
+int qong_nand_rdy(void *chip)
+{
+       udelay(1);
+       return mx31_gpio_get(16);
+}
+
+void qong_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+       if (chip >= 0)
+               mx31_gpio_set(15, 0);
+       else
+               mx31_gpio_set(15, 1);
+
+}
+
+void qong_nand_plat_init(void *chip)
+{
+       struct nand_chip *nand = (struct nand_chip *)chip;
+       nand->chip_delay = 20;
+       nand->select_chip = qong_nand_select_chip;
+       nand->options &= ~NAND_BUSWIDTH_16;
+       board_nand_setup();
+}
+
+#endif