Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx

[karo-tx-uboot.git] / board / eNET / eNET.c

diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 546406a4aa14b800067a3991983ce460a6f4d88a..429fe1b4ff3f6c8886a4f257f88d9e30903c389c 100644 (file)
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/ic/sc520.h>
+#include <asm/arch/sc520.h>
 #include <net.h>
 #include <netdev.h>
 
@@ -35,18 +35,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#undef SC520_CDP_DEBUG
-
-#ifdef SC520_CDP_DEBUG
-#define        PRINTF(fmt,args...)     printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
 unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
 
 static void enet_timer_isr(void);
 static void enet_toggle_run_led(void);
+static void enet_setup_pars(void);
 
 /*
  * Miscellaneous platform dependent initializations
@@ -89,21 +82,7 @@ int board_early_init_f(void)
        /* Clear FPGA program mode */
        writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
 
-       /* Configure Programmable Address Regions */
-       writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[2]);
-       writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[3]);
-       writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[4]);
-       writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[5]);
-       writel(CONFIG_SYS_SC520_SDRAM_PAR, &sc520_mmcr->par[6]);
-       writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[7]);
-       writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[8]);
-       writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[9]);
-       writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[10]);
-       writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[11]);
-       writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[12]);
-       writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[13]);
-/*     writel(CONFIG_SYS_SC520_BOOTCS_PAR, &sc520_mmcr->par14); */
-/*     writel(CONFIG_SYS_SC520_LLIO_PAR, &sc520_mmcr->par15); */
+       enet_setup_pars();
 
        /* Disable Watchdog */
        writew(0x3333, &sc520_mmcr->wdtmrctl);
@@ -128,6 +107,50 @@ int board_early_init_f(void)
        return 0;
 }
 
+static void enet_setup_pars(void)
+{
+       /*
+        * PARs 11 and 12 are 2MB SRAM @ 0x19000000
+        *
+        * These are setup now because older version of U-Boot have them
+        * mapped to a different PAR which gets clobbered which prevents
+        * using SRAM for warm-booting a new image
+        */
+       writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
+       writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
+
+       /* PARs 0 and 1 are Compact Flash slots (4kB each) */
+       writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
+       writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
+
+       /* PAR 2 is used for Cache-As-RAM */
+
+       /*
+        * PARs 5 through 8 are additional NS16550 UARTS
+        * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
+        */
+       writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
+       writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
+       writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
+       writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
+
+       /* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
+       writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
+       writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
+
+       /* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
+       writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
+
+       /*
+        * PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
+        * Already configured in board_init16 (eNET_start16.S)
+        *
+        * PAR 15 is Boot ROM
+        * Already configured in board_init16 (eNET_start16.S)
+        */
+}
+
+
 int board_early_init_r(void)
 {
        /* CPU Speed to 100MHz */
@@ -139,12 +162,6 @@ int board_early_init_r(void)
        return 0;
 }
 
-int dram_init(void)
-{
-       init_sc520_dram();
-       return 0;
-}
-
 void show_boot_progress(int val)
 {
        uchar led_mask;
@@ -168,22 +185,23 @@ int last_stage_init(void)
 
        outb(0x00, LED_LATCH_ADDRESS);
 
-       register_timer_isr (enet_timer_isr);
+       register_timer_isr(enet_timer_isr);
 
        printf("Serck Controls eNET\n");
 
        return 0;
 }
 
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
 {
        if (banknum == 0) {     /* non-CFI boot flash */
                info->portwidth = FLASH_CFI_8BIT;
                info->chipwidth = FLASH_CFI_BY8;
                info->interface = FLASH_CFI_X8;
                return 1;
-       } else
+       } else {
                return 0;
+       }
 }
 
 int board_eth_init(bd_t *bis)
@@ -205,7 +223,7 @@ void setup_pcat_compatibility()
         *  active low polarity on PIC interrupt pins,
         *  active high polarity on all other irq pins
         */
-       writew(0x0000,&sc520_mmcr->intpinpol);
+       writew(0x0000, &sc520_mmcr->intpinpol);
 
        /*
         * PIT 0 -> IRQ0
@@ -234,7 +252,7 @@ void setup_pcat_compatibility()
 
 void enet_timer_isr(void)
 {
-       static long enet_ticks = 0;
+       static long enet_ticks;
 
        enet_ticks++;
 
@@ -263,9 +281,9 @@ void hw_watchdog_reset(void)
 
 void enet_toggle_run_led(void)
 {
-       unsigned char leds_state= inb(LED_LATCH_ADDRESS);
+       unsigned char leds_state = inb(LED_LATCH_ADDRESS);
        if (leds_state & LED_RUN_BITMASK)
-               outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS);
+               outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS);
        else
                outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
 }