#undef FPGA_DEBUG
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);
extern ulong flash_get_size (ulong base, int banknum);
-int flash_banks = CFG_MAX_FLASH_BANKS_DETECT;
+int flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
*/
#include "../common/fpga.c"
-/* Prototypes */
-int gunzip(void *, int, unsigned char *, unsigned long *);
-
#ifdef CONFIG_LCD_USED
/* logo bitmap data - gzip compressed and generated by bin2c */
unsigned char logo_bmp[] =
int board_revision(void)
{
- unsigned long cntrl0Reg;
- volatile unsigned long value;
+ unsigned long CPC0_CR0Reg;
+ unsigned long value;
/*
* Get version of APC405 board from GPIO's
*/
/* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
- cntrl0Reg = mfdcr(cntrl0);
- mtdcr(cntrl0, cntrl0Reg | 0x03800000);
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
/*
* Restore GPIO settings
*/
- mtdcr(cntrl0, cntrl0Reg);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg);
switch (value) {
case 0x001c0000:
* First pull fpga-prg pin low, to disable fpga logic
*/
out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
- out_be32((void*)GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
+ out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
out_be32((void*)GPIO0_OR, 0); /* pull prg low */
/*
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
- mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0 */
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0 */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks
*/
- mtebc(epcr, 0xa8400000); /* ebc always driven */
+ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
/*
* New boards have a single 32MB flash connected to CS0
*/
if (board_revision() >= 8) {
/* disable CS1 */
- mtebc(pb1ap, 0);
- mtebc(pb1cr, 0);
+ mtebc(PB1AP, 0);
+ mtebc(PB1CR, 0);
/* resize CS0 to 32MB */
- mtebc(pb0ap, CFG_EBC_PB0AP_HWREV8);
- mtebc(pb0cr, CFG_EBC_PB0CR_HWREV8);
+ mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
+ mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
}
return 0;
int misc_init_r(void)
{
- u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
- u16 *fpga_ctrl2 =(u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
+ u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
+ u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
unsigned char *dst;
int status;
int index;
int i;
- unsigned long cntrl0Reg;
+ unsigned long CPC0_CR0Reg;
char *str;
uchar *logo_addr;
ulong logo_size;
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
*/
- cntrl0Reg = mfdcr(cntrl0);
- mtdcr(cntrl0, cntrl0Reg | 0x00300000);
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
- dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf("GUNZIP ERROR - must RESET board to recover\n");
do_reset(NULL, 0, 0, NULL);
}
}
/* restore gpio/cs settings */
- mtdcr(cntrl0, cntrl0Reg);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg);
puts("FPGA: ");
/*
* Enable power on PS/2 interface (with reset)
*/
- out_be16(fpga_mode, in_be16(fpga_mode) | CFG_FPGA_CTRL_PS2_RESET);
+ out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
for (i=0;i<100;i++)
udelay(1000);
udelay(1000);
- out_be16(fpga_mode, in_be16(fpga_mode) & ~CFG_FPGA_CTRL_PS2_RESET);
+ out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
/*
* Enable interrupts in exar duart mcr[3]
str = getenv("splashimage");
if (str) {
logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
- logo_size = CFG_VIDEO_LOGO_MAX_SIZE;
+ logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
} else {
logo_addr = logo_bmp;
logo_size = sizeof(logo_bmp);
}
if (gd->board_type >= 6) {
- result = lcd_init((uchar *)CFG_LCD_BIG_REG,
- (uchar *)CFG_LCD_BIG_MEM,
+ result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+ (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13505_640_480_16bpp,
sizeof(regs_13505_640_480_16bpp) /
sizeof(regs_13505_640_480_16bpp[0]),
/* retry with internal image */
logo_addr = logo_bmp;
logo_size = sizeof(logo_bmp);
- lcd_init((uchar *)CFG_LCD_BIG_REG,
- (uchar *)CFG_LCD_BIG_MEM,
+ lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+ (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13505_640_480_16bpp,
sizeof(regs_13505_640_480_16bpp) /
sizeof(regs_13505_640_480_16bpp[0]),
logo_addr, logo_size);
}
} else {
- result = lcd_init((uchar *)CFG_LCD_BIG_REG,
- (uchar *)CFG_LCD_BIG_MEM,
+ result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+ (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_640_480_16bpp,
sizeof(regs_13806_640_480_16bpp) /
sizeof(regs_13806_640_480_16bpp[0]),
/* retry with internal image */
logo_addr = logo_bmp;
logo_size = sizeof(logo_bmp);
- lcd_init((uchar *)CFG_LCD_BIG_REG,
- (uchar *)CFG_LCD_BIG_MEM,
+ lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+ (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_640_480_16bpp,
sizeof(regs_13806_640_480_16bpp) /
sizeof(regs_13806_640_480_16bpp[0]),
* fix environment for field updated units
*/
if (getenv("altbootcmd") == NULL) {
- setenv("usb_load", CFG_USB_LOAD_COMMAND);
- setenv("usbargs", CFG_USB_ARGS);
+ setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
+ setenv("usbargs", CONFIG_SYS_USB_ARGS);
setenv("bootcmd", CONFIG_BOOTCOMMAND);
- setenv("usb_self", CFG_USB_SELF_COMMAND);
- setenv("bootlimit", CFG_BOOTLIMIT);
- setenv("altbootcmd", CFG_ALT_BOOTCOMMAND);
+ setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
+ setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
+ setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
saveenv();
}
int checkboard (void)
{
char str[64];
- int i = getenv_r ("serial#", str, sizeof(str));
+ int i = getenv_f("serial#", str, sizeof(str));
puts ("Board: ");
return 0;
}
-long int initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
- u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+ u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
/*
* Assert or deassert CompactFlash Reset Pin
*/
if (on) {
out_be16(fpga_mode,
- in_be16(fpga_mode) & ~CFG_FPGA_CTRL_CF_RESET);
+ in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
} else {
out_be16(fpga_mode,
- in_be16(fpga_mode) | CFG_FPGA_CTRL_CF_RESET);
+ in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
}
}
#endif /* CONFIG_IDE_RESET */
lxt971_no_sleep();
}
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
int usb_board_init(void)
{
return 0;
usb_board_stop();
return 0;
}
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
projects / karo-tx-uboot.git / blobdiff