Merge branch 'master' of /home/wd/git/u-boot/master

[karo-tx-uboot.git] / board / esd / cms700 / cms700.c

diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
index 9a522b2c0bea2fa48759673763a011ca9413e709..dcd49d4faaa30b5cfef727065998f88fadd48017 100644 (file)
--- a/board/esd/cms700/cms700.c
+++ b/board/esd/cms700/cms700.c
@@ -31,14 +31,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern void lxt971_no_sleep(void);
 
-/* fpga configuration data - not compressed, generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-int filesize = sizeof(fpgadata);
-
-
 int board_early_init_f (void)
 {
        /*
@@ -53,18 +45,18 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
         */
-       mtebc (epcr, 0xa8400000); /* ebc always driven */
+       mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
 
        /*
         * Reset CPLD via GPIO12 (CS3) pin
@@ -104,7 +96,7 @@ int checkboard (void)
 
        puts ("Board: ");
 
-       if (getenv_r("serial#", str, sizeof(str))  == -1) {
+       if (getenv_f("serial#", str, sizeof(str))  == -1) {
                puts ("### No HW ID - assuming CMS700");
        } else {
                puts(str);
@@ -165,7 +157,7 @@ int eeprom_write_enable (unsigned dev_addr, int state)
        return state;
 }
 
-int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
        int query = argc == 1;
        int state = 0;
@@ -197,8 +189,9 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 }
 
 U_BOOT_CMD(eepwren,    2,      0,      do_eep_wren,
-          "Enable / disable / query EEPROM write access",
-          NULL);
+       "Enable / disable / query EEPROM write access",
+       ""
+);
 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 
 /* ------------------------------------------------------------------------- */