DECLARE_GLOBAL_DATA_PTR;
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void __ft_board_setup(void *blob, bd_t *bd);
#undef FPGA_DEBUG
/* Prototypes */
int cpci405_version(void);
-int gunzip(void *, int, unsigned char *, unsigned long *);
void lxt971_no_sleep(void);
int board_early_init_f(void)
* First pull fpga-prg pin low,
* to disable fpga logic (on version 2 board)
*/
- out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
- out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
- out32(GPIO0_OR, 0); /* pull prg low */
+ out_be32((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
+ out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
+ out_be32((void *)GPIO0_OR, 0); /* pull prg low */
/*
* Boot onboard FPGA
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
#if defined(CONFIG_CPCI405_6U)
if (cpci405_version() == 3) {
- mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
+ mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
} else {
- mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
+ mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
}
#else
- mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
+ mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
#endif
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,
* INT0 highest priority */
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}
int cpci405_host(void)
{
- if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
+ if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
return -1; /* yes, board is cpci405 host */
else
return 0; /* no, board is cpci405 adapter */
int cpci405_version(void)
{
- unsigned long cntrl0Reg;
+ unsigned long CPC0_CR0Reg;
unsigned long value;
/*
* Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
*/
- cntrl0Reg = mfdcr(cntrl0);
- mtdcr(cntrl0, cntrl0Reg | 0x03000000);
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
udelay(1000); /* wait some time before reading input */
/*
* Restore GPIO settings
*/
- mtdcr(cntrl0, cntrl0Reg);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg);
switch (value) {
case 0x00180000:
int misc_init_r (void)
{
- unsigned long cntrl0Reg;
+ unsigned long CPC0_CR0Reg;
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
*/
- cntrl0Reg = mfdcr(cntrl0);
- mtdcr(cntrl0, cntrl0Reg | 0x00300000);
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
}
/* restore gpio/cs settings */
- mtdcr(cntrl0, cntrl0Reg);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg);
puts("FPGA: ");
/*
* Select cts (and not dsr) on uart1
*/
- cntrl0Reg = mfdcr(cntrl0);
- mtdcr(cntrl0, cntrl0Reg | 0x00001000);
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
return 0;
}
int len;
#endif
char str[64];
- int i = getenv_r("serial#", str, sizeof(str));
+ int i = getenv_f("serial#", str, sizeof(str));
unsigned short ver;
puts("Board: ");
return result;
}
-int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned short val;
int result;
int i;
unsigned char ow_id[6];
char str[32];
- unsigned char ow_crc;
/*
* Clear 1-wire bit (open drain with pull-up)
OWReadByte(); /* skip family code ( == 0x01) */
for (i = 0; i < 6; i++)
ow_id[i] = OWReadByte();
- ow_crc = OWReadByte(); /* read crc */
+ OWReadByte(); /* read crc */
- sprintf(str, "%08X%04X",
- *(unsigned int *)&ow_id[0],
- *(unsigned short *)&ow_id[4]);
+ sprintf(str, "%02X%02X%02X%02X%02X%02X",
+ ow_id[0], ow_id[1], ow_id[2], ow_id[3], ow_id[4], ow_id[5]);
printf("Setting environment variable 'ow_id' to %s\n", str);
setenv("ow_id", str);
}
U_BOOT_CMD(
onewire, 1, 1, do_onewire,
- "onewire - Read 1-write ID\n",
- NULL
- );
+ "Read 1-write ID",
+ ""
+);
#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
/*
* Write backplane ip-address...
*/
-int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
bd_t *bd = gd->bd;
char *buf;
}
U_BOOT_CMD(
getbpip, 1, 1, do_get_bpip,
- "getbpip - Update IP-Address with Backplane IP-Address\n",
- NULL
- );
+ "Update IP-Address with Backplane IP-Address",
+ ""
+);
/*
* Set and print backplane ip...
*/
-int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *buf;
char str[32];
}
U_BOOT_CMD(
setbpip, 2, 1, do_set_bpip,
- "setbpip - Write Backplane IP-Address\n",
- NULL
- );
+ "Write Backplane IP-Address",
+ ""
+);
#endif /* CONFIG_CPCI405AB */
projects / karo-tx-uboot.git / blobdiff