Merge git://git.denx.de/u-boot-arm

[karo-tx-uboot.git] / board / evb64260 / eth.c

diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c
index eafa48bc6ea97ca837ff9fc5f2c64b82e8dd1377..d7f63bddcbdb0edc12f1c5c42c4ebf0dded05584 100644 (file)
--- a/board/evb64260/eth.c
+++ b/board/evb64260/eth.c
@@ -4,10 +4,7 @@ Skeleton NIC driver for Etherboot
 ***************************************************************************/
 
 /*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2, or (at
- * your option) any later version.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -27,11 +24,12 @@ Skeleton NIC driver for Etherboot
 #include <asm/cache.h>
 #include <miiphy.h>
 #include <net.h>
+#include <netdev.h>
 
 #include "eth.h"
 #include "eth_addrtbl.h"
 
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#if defined(CONFIG_CMD_NET)
 
 #define GT6426x_ETH_BUF_SIZE   1536
 
@@ -88,7 +86,7 @@ static const char ether_port_phy_addr[3]={4,5,6};
 /* MII PHY access routines are common for all i/f, use gal_ent0 */
 #define GT6426x_MII_DEVNAME    "gal_enet0"
 
-int gt6426x_miiphy_read(char *devname, unsigned char phy,
+int gt6426x_miiphy_read(const char *devname, unsigned char phy,
                unsigned char reg, unsigned short *val);
 
 static inline unsigned short
@@ -126,31 +124,32 @@ static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr)
 #endif
 
     if(icr&0x10000000) {
+#ifdef DEBUG
        unsigned int psr;
+
        psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
-#ifdef DEBUG
        printf("PHY state change:\n"
               "  GT:%s:%s:%s:%s\n",
-               psr&1?"100":" 10",
-               psr&8?" Link":"nLink",
-               psr&2?"FD":"HD",
-               psr&4?" FC":"nFC");
+               psr & 1 ? "100" : " 10",
+               psr & 8 ? " Link" : "nLink",
+               psr & 2 ? "FD" : "HD",
+               psr & 4 ? " FC" : "nFC");
 
 #ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */
        {
-       unsigned short mii_11;
-       mii_11=miiphy_read_ret(ether_port_phy_addr[p->dev],0x11);
-
-       printf(" mii:%s:%s:%s:%s %s:%s %s\n",
-               mii_11&(1<<14)?"100":" 10",
-               mii_11&(1<<10)?" Link":"nLink",
-               mii_11&(1<<9)?"FD":"HD",
-               mii_11&(1<<4)?" FC":"nFC",
-
-               mii_11&(1<<7)?"ANc":"ANnc",
-               mii_11&(1<<8)?"AN":"Manual",
-               ""
-               );
+               unsigned short mii_11;
+               mii_11 = miiphy_read_ret(ether_port_phy_addr[p->dev], 0x11);
+
+               printf(" mii:%s:%s:%s:%s %s:%s %s\n",
+                       mii_11 & (1 << 14) ? "100" : " 10",
+                       mii_11 & (1 << 10) ? " Link" : "nLink",
+                       mii_11 & (1 << 9) ? "FD" : "HD",
+                       mii_11 & (1 << 4) ? " FC" : "nFC",
+
+                       mii_11 & (1 << 7) ? "ANc" : "ANnc",
+                       mii_11 & (1 << 8) ? "AN" : "Manual",
+                       ""
+                       );
        }
 #endif /* CONFIG_INTEL_LXT97X */
 #endif /* DEBUG */
@@ -163,7 +162,7 @@ gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr)
        int eth_len=0;
        char *eth_data;
 
-       eth0_rx_desc_single *rx=&p->eth_rx_desc[(p->rdn)];
+       eth0_rx_desc_single *rx = &p->eth_rx_desc[(p->rdn)];
 
        INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
 
@@ -244,15 +243,14 @@ gt6426x_eth_poll(void *v)
 /**************************************************************************
 TRANSMIT - Transmit a frame
 ***************************************************************************/
-int
-gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s)
+int gt6426x_eth_transmit(void *v, char *p, unsigned int s)
 {
        struct eth_device *wp = (struct eth_device *)v;
        struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv;
 #ifdef DEBUG
        unsigned int old_command_stat,old_psr;
 #endif
-       eth0_tx_desc_single *tx=&dev->eth_tx_desc[dev->tdn];
+       eth0_tx_desc_single *tx = &dev->eth_tx_desc[dev->tdn];
 
        /* wait for tx to be ready */
        INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
@@ -344,7 +342,7 @@ gt6426x_eth_disable(void *v)
 MII utilities - write: write to an MII register via SMI
 ***************************************************************************/
 int
-gt6426x_miiphy_write(char *devname, unsigned char phy,
+gt6426x_miiphy_write(const char *devname, unsigned char phy,
                unsigned char reg, unsigned short data)
 {
     unsigned int temp= (reg<<21) | (phy<<16) | data;
@@ -359,7 +357,7 @@ gt6426x_miiphy_write(char *devname, unsigned char phy,
 MII utilities - read: read from an MII register via SMI
 ***************************************************************************/
 int
-gt6426x_miiphy_read(char *devname, unsigned char phy,
+gt6426x_miiphy_read(const char *devname, unsigned char phy,
                unsigned char reg, unsigned short *val)
 {
     unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
@@ -421,24 +419,24 @@ gt6426x_dump_mii(bd_t *bis, unsigned short phy)
 static void
 check_phy_state(struct eth_dev_s *p)
 {
-       int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_BMSR);
+       int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_BMSR);
        int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
 
-       if ((psr & 1<<3) && (bmsr & PHY_BMSR_LS)) {
-               int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANAR) &
-                               miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANLPAR);
+       if ((psr & 1<<3) && (bmsr & BMSR_LSTATUS)) {
+               int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_ADVERTISE) &
+                               miiphy_read_ret(ether_port_phy_addr[p->dev], MII_LPA);
                int want;
 
-               if (nego & PHY_ANLPAR_TXFD) {
+               if (nego & LPA_100FULL) {
                        want = 0x3;
                        printf("MII: 100Base-TX, Full Duplex\n");
-               } else if (nego & PHY_ANLPAR_TX) {
+               } else if (nego & LPA_100HALF) {
                        want = 0x1;
                        printf("MII: 100Base-TX, Half Duplex\n");
-               } else if (nego & PHY_ANLPAR_10FD) {
+               } else if (nego & LPA_10FULL) {
                        want = 0x2;
                        printf("MII: 10Base-T, Full Duplex\n");
-               } else if (nego & PHY_ANLPAR_10) {
+               } else if (nego & LPA_10HALF) {
                        want = 0x0;
                        printf("MII: 10Base-T, Half Duplex\n");
                } else {
@@ -529,7 +527,7 @@ gt6426x_eth_probe(void *v, bd_t *bis)
 #endif
 
        /* 31  28 27  24 23  20 19  16
-        *  0000   0000   0000   0000   [0004]
+        *  0000   0000   0000   0000   [0004]
         * 15  12 11  8   7  4   3  0
         *  1000   1101   0000   0000   [4d00]
         *    20 - 0=MII 1=RMII
@@ -684,7 +682,7 @@ gt6426x_eth_initialize(bd_t *bis)
                        return;
                }
 
-               /* must be less than NAMESIZE (16) */
+               /* must be less than sizeof(dev->name) */
                sprintf(dev->name, "gal_enet%d", devnum);
 
 #ifdef DEBUG
@@ -707,7 +705,7 @@ gt6426x_eth_initialize(bd_t *bis)
                                return;
                }
 
-               temp = getenv_r (s, buf, sizeof(buf));
+               temp = getenv_f(s, buf, sizeof(buf));
                s = (temp > 0) ? buf : NULL;
 
 #ifdef DEBUG
@@ -797,11 +795,11 @@ gt6426x_eth_initialize(bd_t *bis)
 
 
                eth_register(dev);
-#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
                miiphy_register(dev->name,
                                gt6426x_miiphy_read, gt6426x_miiphy_write);
 #endif
        }
 
 }
-#endif /* CFG_CMD_NET && CONFIG_NET_MULTI */
+#endif