B4860qds: Set SerDes2 refclk2 at to 156.25MHz for XFI to work

[karo-tx-uboot.git] / board / freescale / b4860qds / b4860qds.c

diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index 9d51864fbbd6898f598619630a011a66722ea9cb..24a709e25793b78408d27d730159d25363447e01 100644 (file)
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -29,7 +29,6 @@
 
 #define CLK_MUX_SEL_MASK       0x4
 #define ETH_PHY_CLK_OUT                0x4
-#define PLL_NUM                        2
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -121,6 +120,7 @@ int configure_vsc3316_3308(void)
        debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
 
        switch (serdes1_prtcl) {
+       case 0x29:
        case 0x2a:
        case 0x2C:
        case 0x2D:
@@ -200,6 +200,7 @@ int configure_vsc3316_3308(void)
                break;
 
 #ifdef CONFIG_PPC_B4420
+       case 0x17:
        case 0x18:
                        /*
                         * Configuration:
@@ -384,7 +385,7 @@ int config_serdes1_refclks(void)
                /* Steps For SerDes PLLs reset and reconfiguration after
                 * changing SerDes's refclks
                 */
-               for (i = 0; i < PLL_NUM; i++) {
+               for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
                        debug("For PLL%d reset and reconfiguration after"
                               " changing refclks\n", i+1);
                        clrbits_be32(&srds_regs->bank[i].rstctl,
@@ -451,7 +452,7 @@ int config_serdes2_refclks(void)
                if (!ret) {
                        ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
                                        SERDES_REFCLK_100,
-                                       SERDES_REFCLK_100, 0);
+                                       SERDES_REFCLK_156_25, 0);
                        if (ret) {
                                printf("IDT8T49N222A configuration failed.\n");
                                goto out;
@@ -465,7 +466,7 @@ int config_serdes2_refclks(void)
                /* Steps For SerDes PLLs reset and reconfiguration after
                 * changing SerDes's refclks
                 */
-               for (i = 0; i < PLL_NUM; i++) {
+               for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
                        clrbits_be32(&srds2_regs->bank[i].rstctl,
                                        SRDS_RSTCTL_SDRST_B);
                        udelay(10);