Merge 'u-boot-atmel/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / board / freescale / mpc8540ads / mpc8540ads.c

diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 7dccd3735924e7b06c77a3dd635984b35ae2ec0c..418c06b655cacaec5961435189b3ae541d1febe0 100644 (file)
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -39,18 +39,16 @@ extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
 void local_bus_init(void);
-void sdram_init(void);
-long int fixed_sdram(void);
 
 int checkboard (void)
 {
        puts("Board: ADS\n");
 
 #ifdef CONFIG_PCI
-       printf("    PCI1: 32 bit, %d MHz (compiled)\n",
+       printf("PCI1: 32 bit, %d MHz (compiled)\n",
               CONFIG_SYS_CLK_FREQ / 1000000);
 #else
-       printf("    PCI1: disabled\n");
+       printf("PCI1: disabled\n");
 #endif
 
        /*
@@ -61,54 +59,6 @@ int checkboard (void)
        return 0;
 }
 
-
-phys_size_t
-initdram(int board_type)
-{
-       long dram_size = 0;
-
-       puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
-       {
-           volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-           uint temp_ddrdll = 0;
-
-           /*
-            * Work around to stabilize DDR DLL
-            */
-           temp_ddrdll = gur->ddrdllcr;
-           gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
-           asm("sync;isync;msync");
-       }
-#endif
-
-#ifdef CONFIG_SPD_EEPROM
-       dram_size = fsl_ddr_sdram();
-       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
-       dram_size *= 0x100000;
-#else
-       dram_size = fixed_sdram();
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-       /*
-        * Initialize and enable DDR ECC.
-        */
-       ddr_enable_ecc(dram_size);
-#endif
-
-       /*
-        * Initialize SDRAM.
-        */
-       sdram_init();
-
-       puts("    DDR: ");
-       return dram_size;
-}
-
-
 /*
  * Initialize Local Bus
  */
@@ -117,7 +67,7 @@ void
 local_bus_init(void)
 {
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+       volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
        uint clkdiv;
        uint lbc_hz;
@@ -127,20 +77,20 @@ local_bus_init(void)
         * Errata LBC11.
         * Fix Local Bus clock glitch when DLL is enabled.
         *
-        * If localbus freq is < 66Mhz, DLL bypass mode must be used.
-        * If localbus freq is > 133Mhz, DLL can be safely enabled.
+        * If localbus freq is < 66MHz, DLL bypass mode must be used.
+        * If localbus freq is > 133MHz, DLL can be safely enabled.
         * Between 66 and 133, the DLL is enabled with an override workaround.
         */
 
        get_sys_info(&sysinfo);
-       clkdiv = lbc->lcrr & 0x0f;
+       clkdiv = lbc->lcrr & LCRR_CLKDIV;
        lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
        if (lbc_hz < 66) {
-               lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;   /* DLL Bypass */
+               lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;    /* DLL Bypass */
 
        } else if (lbc_hz >= 133) {
-               lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+               lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
 
        } else {
                /*
@@ -155,7 +105,7 @@ local_bus_init(void)
                        lbc->lcrr = 0x10000004;
                }
 
-               lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+               lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
                udelay(200);
 
                /*
@@ -172,21 +122,20 @@ local_bus_init(void)
 /*
  * Initialize SDRAM memory on the Local Bus.
  */
-
-void
-sdram_init(void)
+void lbc_sdram_init(void)
 {
-       volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+       volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
        uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
-       puts("    SDRAM: ");
-       print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+       puts("LBC SDRAM: ");
+       print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+                  "\n       ");
 
        /*
         * Setup SDRAM Base and Option Registers
         */
-       lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-       lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+       set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+       set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
        lbc->lbcr = CONFIG_SYS_LBC_LBCR;
        asm("msync");
 
@@ -232,10 +181,10 @@ sdram_init(void)
 /*************************************************************************
  *  fixed sdram init -- doesn't use serial presence detect.
  ************************************************************************/
-long int fixed_sdram (void)
+phys_size_t fixed_sdram(void)
 {
   #ifndef CONFIG_SYS_RAMBOOT
-       volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+       volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
 
        ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
        ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;