debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
- printf (" eTSEC1 is in sgmii mode.\n");
+ printf("eTSEC1 is in sgmii mode.\n");
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
- printf (" eTSEC2 is in sgmii mode.\n");
+ printf("eTSEC2 is in sgmii mode.\n");
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
- printf (" eTSEC3 is in sgmii mode.\n");
+ printf("eTSEC3 is in sgmii mode.\n");
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
- printf (" eTSEC4 is in sgmii mode.\n");
+ printf("eTSEC4 is in sgmii mode.\n");
puts("\n");
#ifdef CONFIG_PCIE3
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
SET_STD_PCIE_INFO(pci_info[num], 3);
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
- printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
/*
in_be32(p);
}
} else {
- printf (" PCIE3: disabled\n");
+ printf("PCIE3: disabled\n");
}
puts("\n");
#else
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
- printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
- pcie_ep ? "Endpoint" : "Root Complex",
- pci_info[num].regs);
+ printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
} else {
- printf (" PCIE2: disabled\n");
+ printf("PCIE2: disabled\n");
}
puts("\n");
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
+ printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
- printf (" PCIE1: disabled\n");
+ printf("PCIE1: disabled\n");
}
puts("\n");
fdt_fixup_memory(blob, (u64)base, (u64)size);
-#ifdef CONFIG_PCIE3
- ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
-#endif
-#ifdef CONFIG_PCIE2
- ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#endif
+ FT_FSL_PCI_SETUP;
+
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif