/*
- * Copyright 2006, 2007 Freescale Semiconductor.
+ * Copyright 2006, 2007, 2010 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <fdt_support.h>
#include <netdev.h>
-#include "../common/pixis.h"
-
phys_size_t fixed_sdram(void);
int board_early_init_f(void)
return 0;
}
+const char *board_hwconfig = "foo:bar=baz";
+const char *cpu_hwconfig = "foo:bar=baz";
phys_size_t
initdram(int board_type)
dram_size = fixed_sdram();
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- puts(" DDR: ");
- return dram_size;
-#endif
+ setup_ddr_bat(dram_size);
puts(" DDR: ");
return dram_size;
#if defined(CONFIG_PCI)
-static struct pci_controller pci1_hose;
+static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCI */
-#ifdef CONFIG_PCI2
-static struct pci_controller pci2_hose;
-#endif /* CONFIG_PCI2 */
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif /* CONFIG_PCIE2 */
int first_free_busno = 0;
void pci_init_board(void)
{
-#ifdef CONFIG_PCI1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- struct pci_controller *hose = &pci1_hose;
- struct pci_region *r = hose->regions;
+ struct fsl_pci_info pci_info[2];
+ int pcie_ep;
+ int num = 0;
+
+#ifdef CONFIG_PCIE1
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
- uint devdisr = gur->devdisr;
+ uint devdisr = in_be32(&gur->devdisr);
uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
+ int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-#ifdef DEBUG
- uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
- >> MPC8641_PORBMSR_HA_SHIFT;
- uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
-#endif
- if ((io_sel == 2 || io_sel == 3 || io_sel == 5
- || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
- && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
- debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
- debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug(" with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- debug("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BUS,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BUS,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno=first_free_busno;
- pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
-
- fsl_pci_init(hose);
-
- first_free_busno=hose->last_busno+1;
- printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
/*
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
*/
- in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT
- + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
+ in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
+ + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
} else {
- puts("PCI-EXPRESS 1: Disabled\n");
+ puts("PCIE1: disabled\n");
}
-}
#else
- puts("PCI-EXPRESS1: Disabled\n");
-#endif /* CONFIG_PCI1 */
-
-#ifdef CONFIG_PCI2
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
- struct pci_controller *hose = &pci2_hose;
- struct pci_region *r = hose->regions;
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCI2_MEM_BUS,
- CONFIG_SYS_PCI2_MEM_PHYS,
- CONFIG_SYS_PCI2_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCI2_IO_BUS,
- CONFIG_SYS_PCI2_IO_PHYS,
- CONFIG_SYS_PCI2_IO_SIZE,
- PCI_REGION_IO);
-
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno=first_free_busno;
- pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
-
- fsl_pci_init(hose);
-
- first_free_busno=hose->last_busno+1;
- printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
-}
+ puts("PCIE1: disabled\n");
+#endif /* CONFIG_PCIE1 */
+
+#ifdef CONFIG_PCIE2
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+ printf("PCIE2: connected as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie2_hose, first_free_busno);
#else
- puts("PCI-EXPRESS 2: Disabled\n");
-#endif /* CONFIG_PCI2 */
+ puts("PCIE2: disabled\n");
+#endif /* CONFIG_PCIE2 */
}
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI1
- ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCI2
- ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
-#endif
+ FT_FSL_PCI_SETUP;
/*
* Warn if it looks like the device tree doesn't match u-boot.
projects / karo-tx-uboot.git / blobdiff