#include <asm/arch/mx5x_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/clock.h>
#include <asm/errno.h>
+#include <asm/imx-common/mx5_video.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/gpio.h>
+#include <power/pmic.h>
+#include <dialog_pmic.h>
+#include <fsl_pmic.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
-DECLARE_GLOBAL_DATA_PTR;
+#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
-u32 get_board_rev(void)
-{
- return get_cpu_rev();
-}
+DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}
+u32 get_board_rev(void)
+{
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ struct fuse_bank *bank = &iim->bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank->fuse_regs;
+
+ int rev = readl(&fuse->gp[6]);
+
+ if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
+ rev = 0;
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
static void setup_iomux_uart(void)
{
/* UART1 RXD */
PAD_CTL_ODE_OPENDRAIN_ENABLE);
}
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+ /* request VBUS power enable pin, GPIO7_8 */
+ mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
+ gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
+ return 0;
+}
+#endif
+
static void setup_iomux_fec(void)
{
/*FEC_MDIO*/
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR, 1},
- {MMC_SDHC3_BASE_ADDR, 1},
+ {MMC_SDHC1_BASE_ADDR},
+ {MMC_SDHC3_BASE_ADDR},
};
-int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret;
+
+ mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
+ gpio_direction_input(IMX_GPIO_NR(3, 11));
+ mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
+ gpio_direction_input(IMX_GPIO_NR(3, 13));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- *cd = gpio_get_value(77); /*GPIO3_13*/
+ ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
else
- *cd = gpio_get_value(75); /*GPIO3_11*/
+ ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
- return 0;
+ return ret;
}
int board_mmc_init(bd_t *bis)
u32 index;
s32 status = 0;
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
switch (index) {
case 0:
}
#endif
+static void setup_iomux_i2c(void)
+{
+ /* I2C1 SDA */
+ mxc_request_iomux(MX53_PIN_CSI0_D8,
+ IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
+ PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+ PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ /* I2C1 SCL */
+ mxc_request_iomux(MX53_PIN_CSI0_D9,
+ IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
+ PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+ PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE);
+}
+
+static int power_init(void)
+{
+ unsigned int val;
+ int ret = -1;
+ struct pmic *p;
+ int retval;
+
+ if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
+ retval = pmic_dialog_init(I2C_PMIC);
+ if (retval)
+ return retval;
+
+ p = pmic_get("DIALOG_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ /* Set VDDA to 1.25V */
+ val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
+ ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
+
+ ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
+ val |= DA9052_SUPPLY_VBCOREGO;
+ ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
+
+ /* Set Vcc peripheral to 1.30V */
+ ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
+ ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
+ }
+
+ if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
+ retval = pmic_init(I2C_PMIC);
+ if (retval)
+ return retval;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ /* Set VDDGP to 1.25V for 1GHz on SW1 */
+ pmic_reg_read(p, REG_SW_0, &val);
+ val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
+ ret = pmic_reg_write(p, REG_SW_0, val);
+
+ /* Set VCC as 1.30V on SW2 */
+ pmic_reg_read(p, REG_SW_1, &val);
+ val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
+ ret |= pmic_reg_write(p, REG_SW_1, val);
+
+ /* Set global reset timer to 4s */
+ pmic_reg_read(p, REG_POWER_CTL2, &val);
+ val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
+ ret |= pmic_reg_write(p, REG_POWER_CTL2, val);
+
+ /* Set VUSBSEL and VUSBEN for USB PHY supply*/
+ pmic_reg_read(p, REG_MODE_0, &val);
+ val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
+ ret |= pmic_reg_write(p, REG_MODE_0, val);
+
+ /* Set SWBST to 5V in auto mode */
+ val = SWBST_AUTO;
+ ret |= pmic_reg_write(p, SWBST_CTRL, val);
+ }
+
+ return ret;
+}
+
+static void clock_1GHz(void)
+{
+ int ret;
+ u32 ref_clk = MXC_HCLK;
+ /*
+ * After increasing voltage to 1.25V, we can switch
+ * CPU clock to 1GHz and DDR to 400MHz safely
+ */
+ ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
+ if (ret)
+ printf("CPU: Switch CPU clock to 1GHZ failed\n");
+
+ ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+ ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+ if (ret)
+ printf("CPU: Switch DDR clock to 400MHz failed\n");
+}
+
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_fec();
+ setup_iomux_lcd();
return 0;
}
+int print_cpuinfo(void)
+{
+ u32 cpurev;
+
+ cpurev = get_cpu_rev();
+ printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
+ (cpurev & 0xFF000) >> 12,
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ printf("Reset cause: %s\n", get_reset_cause());
+ return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+ mxc_set_sata_internal_clock();
+ setup_iomux_i2c();
+ if (!power_init())
+ clock_1GHz();
+ print_cpuinfo();
+
+ lcd_enable();
+
return 0;
}
projects / karo-tx-uboot.git / blobdiff