Unified codebase for TX28, TX48, TX51, TX53

[karo-tx-uboot.git] / board / freescale / mx53loco / mx53loco.c

diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index d736141e287ff8c68589292bccdea0bd05805743..dec966ddd6aa3caeaa377645101d13b9e35a3e64 100644 (file)
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -27,6 +27,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/clock.h>
 #include <asm/errno.h>
@@ -35,6 +36,9 @@
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <asm/gpio.h>
+#include <pmic.h>
+#include <dialog_pmic.h>
+#include <fsl_pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -58,6 +62,18 @@ void dram_init_banksize(void)
        gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 }
 
+u32 get_board_rev(void)
+{
+       struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+       struct fuse_bank *bank = &iim->bank[0];
+       struct fuse_bank0_regs *fuse =
+               (struct fuse_bank0_regs *)bank->fuse_regs;
+
+       int rev = readl(&fuse->gp[6]);
+
+       return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
 static void setup_iomux_uart(void)
 {
        /* UART1 RXD */
@@ -81,10 +97,9 @@ static void setup_iomux_uart(void)
 #ifdef CONFIG_USB_EHCI_MX5
 int board_ehci_hcd_init(int port)
 {
-       /* request VBUS power enable pin, GPIO[8}, gpio7 */
+       /* request VBUS power enable pin, GPIO7_8 */
        mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
-       gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0);
-       gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
+       gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
        return 0;
 }
 #endif
@@ -290,6 +305,103 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+static void setup_iomux_i2c(void)
+{
+       /* I2C1 SDA */
+       mxc_request_iomux(MX53_PIN_CSI0_D8,
+               IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+       mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
+               INPUT_CTL_PATH0);
+       mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
+               PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+               PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
+               PAD_CTL_PUE_PULL |
+               PAD_CTL_ODE_OPENDRAIN_ENABLE);
+       /* I2C1 SCL */
+       mxc_request_iomux(MX53_PIN_CSI0_D9,
+               IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+       mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
+               INPUT_CTL_PATH0);
+       mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
+               PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+               PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
+               PAD_CTL_PUE_PULL |
+               PAD_CTL_ODE_OPENDRAIN_ENABLE);
+}
+
+static int power_init(void)
+{
+       unsigned int val;
+       int ret = -1;
+       struct pmic *p;
+
+       if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
+               pmic_dialog_init();
+               p = get_pmic();
+
+               /* Set VDDA to 1.25V */
+               val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
+               ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
+
+               ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
+               val |= DA9052_SUPPLY_VBCOREGO;
+               ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
+
+               /* Set Vcc peripheral to 1.30V */
+               ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
+               ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
+       }
+
+       if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
+               pmic_init();
+               p = get_pmic();
+
+               /* Set VDDGP to 1.25V for 1GHz on SW1 */
+               pmic_reg_read(p, REG_SW_0, &val);
+               val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
+               ret = pmic_reg_write(p, REG_SW_0, val);
+
+               /* Set VCC as 1.30V on SW2 */
+               pmic_reg_read(p, REG_SW_1, &val);
+               val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
+               ret |= pmic_reg_write(p, REG_SW_1, val);
+
+               /* Set global reset timer to 4s */
+               pmic_reg_read(p, REG_POWER_CTL2, &val);
+               val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
+               ret |= pmic_reg_write(p, REG_POWER_CTL2, val);
+
+               /* Set VUSBSEL and VUSBEN for USB PHY supply*/
+               pmic_reg_read(p, REG_MODE_0, &val);
+               val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
+               ret |= pmic_reg_write(p, REG_MODE_0, val);
+
+               /* Set SWBST to 5V in auto mode */
+               val = SWBST_AUTO;
+               ret |= pmic_reg_write(p, SWBST_CTRL, val);
+       }
+
+       return ret;
+}
+
+static void clock_1GHz(void)
+{
+       int ret;
+       u32 ref_clk = CONFIG_SYS_MX5_HCLK;
+       /*
+        * After increasing voltage to 1.25V, we can switch
+        * CPU clock to 1GHz and DDR to 400MHz safely
+        */
+       ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
+       if (ret)
+               printf("CPU:   Switch CPU clock to 1GHZ failed\n");
+
+       ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+       ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+       if (ret)
+               printf("CPU:   Switch DDR clock to 400MHz failed\n");
+}
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();
@@ -298,10 +410,38 @@ int board_early_init_f(void)
        return 0;
 }
 
+int print_cpuinfo(void)
+{
+       u32 cpurev;
+
+       cpurev = get_cpu_rev();
+       printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
+               (cpurev & 0xFF000) >> 12,
+               (cpurev & 0x000F0) >> 4,
+               (cpurev & 0x0000F) >> 0,
+               mxc_get_clock(MXC_ARM_CLK) / 1000000);
+       printf("Reset cause: %s\n", get_reset_cause());
+       return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+       setup_iomux_i2c();
+       if (!power_init())
+               clock_1GHz();
+       print_cpuinfo();
+
+       return 0;
+}
+#endif
+
 int board_init(void)
 {
        gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
+       mxc_set_sata_internal_clock();
+
        return 0;
 }