imx: mx6q/dlsabreauto: And NAND flash support

[karo-tx-uboot.git] / board / freescale / mx6qsabreauto / mx6qsabreauto.c

diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 42ae6fac5e2a258d64550be1eedbd12a1ed931f8..c35dcaf3cf0c400ed802441c523e40b7e93b9fea 100644 (file)
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -46,6 +46,11 @@ DECLARE_GLOBAL_DATA_PTR;
        PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
        PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+                       PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 
 int dram_init(void)
@@ -200,6 +205,63 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t gpmi_pads[] = {
+       MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
+       MX6_PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
+};
+
+static void setup_gpmi_nand(void)
+{
+       struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+       /* config gpmi nand iomux */
+       imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+       /* gate ENFC_CLK_ROOT clock first,before clk source switch */
+       clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+       clrbits_le32(&mxc_ccm->CCGR4,
+               MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+       /* config gpmi and bch clock to 100 MHz */
+       clrsetbits_le32(&mxc_ccm->cs2cdr,
+                       MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+                       MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+                       MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+                       MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+                       MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+                       MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+       /* enable ENFC_CLK_ROOT clock */
+       setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+       /* enable gpmi and bch clock gating */
+       setbits_le32(&mxc_ccm->CCGR4,
+                    MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+                    MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+                    MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+                    MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+                    MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+       /* enable apbh clock gating */
+       setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
 int mx6_rgmii_rework(struct phy_device *phydev)
 {
        unsigned short val;
@@ -336,6 +398,10 @@ int board_early_init_f(void)
 #ifdef CONFIG_VIDEO_IPUV3
        setup_display();
 #endif
+
+#ifdef CONFIG_NAND_MXS
+       setup_gpmi_nand();
+#endif
        return 0;
 }