Merge branch 'master' of git://git.denx.de/u-boot-usb
[karo-tx-uboot.git] / board / freescale / mx6sxsabresd / mx6sxsabresd.c
index 02e82b2..fd8bc72 100644 (file)
@@ -25,6 +25,7 @@
 #include <netdev.h>
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
 #include <usb.h>
 #include <usb/ehci-fsl.h>
 
@@ -70,6 +71,34 @@ static iomux_v3_cfg_t const uart1_pads[] = {
        MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+       MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+       MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+       /* CD pin */
+       MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+       /* RST_B, used for power reset cycle */
+       MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
 static iomux_v3_cfg_t const usdhc4_pads[] = {
        MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -121,7 +150,6 @@ static int setup_fec(void)
 {
        struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
        struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-       int ret;
        int reg;
 
        /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
@@ -142,11 +170,7 @@ static int setup_fec(void)
        reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
        writel(reg, &anatop->pll_enet);
 
-       ret = enable_fec_anatop_clock(ENET_125MHz);
-       if (ret)
-               return ret;
-
-       return 0;
+       return enable_fec_anatop_clock(ENET_125MHZ);
 }
 
 int board_eth_init(bd_t *bis)
@@ -172,57 +196,67 @@ static struct i2c_pads_info i2c_pad_info1 = {
        },
 };
 
-static int pfuze_init(void)
+int power_init_board(void)
 {
        struct pmic *p;
-       int ret;
        unsigned int reg;
 
-       ret = power_pfuze100_init(I2C_PMIC);
-       if (ret)
-               return ret;
-
-       p = pmic_get("PFUZE100");
-       ret = pmic_probe(p);
-       if (ret)
-               return ret;
-
-       pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
-       printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
-
-       /* Set SW1AB standby voltage to 0.975V */
-       pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
-       reg &= ~0x3f;
-       reg |= 0x1b;
-       pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
-
-       /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
-       pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
-       reg &= ~0xc0;
-       reg |= 0x40;
-       pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
-
-       /* Set SW1C standby voltage to 0.975V */
-       pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
-       reg &= ~0x3f;
-       reg |= 0x1b;
-       pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
-
-       /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
-       pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
-       reg &= ~0xc0;
-       reg |= 0x40;
-       pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+       p = pfuze_common_init(I2C_PMIC);
+       if (!p)
+               return -ENODEV;
 
        /* Enable power of VGEN5 3V3, needed for SD3 */
        pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
-       reg &= ~0x1F;
-       reg |= 0x1F;
+       reg &= ~LDO_VOL_MASK;
+       reg |= (LDOB_3_30V | (1 << LDO_EN));
        pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
 
        return 0;
 }
 
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET   0x800
+#define UCTRL_PWR_POL          (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+       /* OGT1 */
+       MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+       MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+       /* OTG2 */
+       MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+       imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+                                        ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+       if (port == 1)
+               return USB_INIT_HOST;
+       else
+               return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+       u32 *usbnc_usb_ctrl;
+
+       if (port > 1)
+               return -EINVAL;
+
+       usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+                                port * 4);
+
+       /* Set Power polarity */
+       setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+       return 0;
+}
+#endif
+
 int board_phy_config(struct phy_device *phydev)
 {
        /*
@@ -245,7 +279,6 @@ int board_phy_config(struct phy_device *phydev)
 int board_early_init_f(void)
 {
        setup_iomux_uart();
-       setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 
        /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
        imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
@@ -261,78 +294,97 @@ int board_early_init_f(void)
        return 0;
 }
 
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+       {USDHC2_BASE_ADDR, 0, 4},
+       {USDHC3_BASE_ADDR},
        {USDHC4_BASE_ADDR},
 };
 
+#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC3_PWR_GPIO        IMX_GPIO_NR(2, 11)
+#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
+
 int board_mmc_getcd(struct mmc *mmc)
 {
-       return 1;       /* Assume boot SD always present */
+       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+       int ret = 0;
+
+       switch (cfg->esdhc_base) {
+       case USDHC2_BASE_ADDR:
+               ret = 1; /* Assume uSDHC2 is always present */
+               break;
+       case USDHC3_BASE_ADDR:
+               ret = !gpio_get_value(USDHC3_CD_GPIO);
+               break;
+       case USDHC4_BASE_ADDR:
+               ret = !gpio_get_value(USDHC4_CD_GPIO);
+               break;
+       }
+
+       return ret;
 }
 
 int board_mmc_init(bd_t *bis)
 {
-       imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-
-       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-       return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-
-#ifdef CONFIG_USB_EHCI_MX6
-#define USB_OTHERREGS_OFFSET   0x800
-#define UCTRL_PWR_POL          (1 << 9)
-
-static iomux_v3_cfg_t const usb_otg_pads[] = {
-       /* OGT1 */
-       MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
-       /* OTG2 */
-       MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
-};
-
-static void setup_usb(void)
-{
-       imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
-                                        ARRAY_SIZE(usb_otg_pads));
-}
-
-int board_usb_phy_mode(int port)
-{
-       if (port == 1)
-               return USB_INIT_HOST;
-       else
-               return usb_phy_mode(port);
-}
-
-int board_ehci_hcd_init(int port)
-{
-       u32 *usbnc_usb_ctrl;
-
-       if (port > 1)
-               return -EINVAL;
-
-       usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
-                                port * 4);
+       int i, ret;
 
-       /* Set Power polarity */
-       setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+       /*
+        * According to the board_mmc_init() the following map is done:
+        * (U-boot device node)    (Physical Port)
+        * mmc0                    USDHC2
+        * mmc1                    USDHC3
+        * mmc2                    USDHC4
+        */
+       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+               switch (i) {
+               case 0:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+                       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+                       break;
+               case 1:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+                       gpio_direction_input(USDHC3_CD_GPIO);
+                       gpio_direction_output(USDHC3_PWR_GPIO, 1);
+                       usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+                       break;
+               case 2:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+                       gpio_direction_input(USDHC4_CD_GPIO);
+                       usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+                       break;
+               default:
+                       printf("Warning: you configured more USDHC controllers"
+                               "(%d) than supported by the board\n", i + 1);
+                       return -EINVAL;
+                       }
+
+                       ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+                       if (ret) {
+                               printf("Warning: failed to initialize mmc dev %d\n", i);
+                               return ret;
+                       }
+       }
 
        return 0;
 }
-#endif
 
 int board_init(void)
 {
        /* Address of boot parameters */
        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_SYS_I2C_MXC
+       setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
        return 0;
 }
 
 int board_late_init(void)
 {
-       pfuze_init();
-
        return 0;
 }