Merge branch 'master' of git://git.denx.de/u-boot-microblaze

[karo-tx-uboot.git] / board / freescale / p1_p2_rdb / ddr.c

diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 853044e1cfa70f3eef7f01be8c78efd0aed02e1b..916439c17f2afdb8300722fa4f17aeacee650b95 100644 (file)
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -74,13 +74,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #define CONFIG_SYS_DDR_INTERVAL_667    0x0a280100
 
 #define CONFIG_SYS_DDR_TIMING_3_800    0x00040000
-#define CONFIG_SYS_DDR_TIMING_0_800    0x55770802
+#define CONFIG_SYS_DDR_TIMING_0_800    0x00770802
 #define CONFIG_SYS_DDR_TIMING_1_800    0x6f6b6543
 #define CONFIG_SYS_DDR_TIMING_2_800    0x0fa074d1
 #define CONFIG_SYS_DDR_CLK_CTRL_800    0x02800000
 #define CONFIG_SYS_DDR_MODE_1_800      0x00040852
 #define CONFIG_SYS_DDR_MODE_2_800      0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_800    0x0a280100
+#define CONFIG_SYS_DDR_INTERVAL_800    0x0c300100
 
 fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
        .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
@@ -204,8 +204,7 @@ phys_size_t fixed_sdram (void)
 
        cpu = gd->cpu;
        /* P1020 and it's derivatives support max 32bit DDR width */
-       if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
-               cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
+       if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
                ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
        } else {
                ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
@@ -232,8 +231,7 @@ phys_size_t fixed_sdram (void)
                                        strmhz(buf, ddr_freq));
 
        /* P1020 and it's derivatives support max 32bit DDR width */
-       if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
-               cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
+       if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
                ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
                ddr_cfg_regs.cs[0].bnds = 0x0000001F;
        }