Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'

[karo-tx-uboot.git] / board / freescale / p1_p2_rdb / ddr.c

diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 71c60888ac1d546673a8c9f1b97eda91ea630681..98ee5f10215ab961e44a083a9855248ffe2e2ff2 100644 (file)
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -1,30 +1,14 @@
 /*
  * Copyright 2009, 2011 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <asm/fsl_law.h>
 
@@ -196,28 +180,22 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
 
 phys_size_t fixed_sdram (void)
 {
-       char buf[32];
        fsl_ddr_cfg_regs_t ddr_cfg_regs;
        size_t ddr_size;
        struct cpu_type *cpu;
        ulong ddr_freq, ddr_freq_mhz;
 
-       cpu = gd->cpu;
-       /* P1020 and it's derivatives support max 32bit DDR width */
-       if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
-               cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
-               ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
-       } else {
-               ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-       }
+       cpu = gd->arch.cpu;
+
+       ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
 #if defined(CONFIG_SYS_RAMBOOT)
        return ddr_size;
 #endif
        ddr_freq = get_ddr_freq(0);
        ddr_freq_mhz = ddr_freq / 1000000;
 
-       printf("Configuring DDR for %s MT/s data rate\n",
-                               strmhz(buf, ddr_freq));
+       printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
 
        if(ddr_freq_mhz <= 400)
                memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
@@ -228,17 +206,15 @@ phys_size_t fixed_sdram (void)
        else if(ddr_freq_mhz <= 800)
                memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
        else
-               panic("Unsupported DDR data rate %s MT/s data rate\n",
-                                       strmhz(buf, ddr_freq));
+               panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
 
        /* P1020 and it's derivatives support max 32bit DDR width */
-       if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
-               cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
+       if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
                ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
                ddr_cfg_regs.cs[0].bnds = 0x0000001F;
        }
 
-       fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+       fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 
        set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
        return ddr_size;