Merge branch 'master' of git://git.denx.de/u-boot-x86

[karo-tx-uboot.git] / board / freescale / p1_p2_rdb / ddr.c

diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 37c4b0a3ba939bc8317b72fe700ad0f8358eff99..b16b8c8a902afd319e45fa9ca93b910ff7c4c4ef 100644 (file)
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009, 2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -30,14 +30,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-                                  unsigned int ctrl_num);
-
-#define DATARATE_400MHZ 400000000
-#define DATARATE_533MHZ 533333333
-#define DATARATE_667MHZ 666666666
-#define DATARATE_800MHZ 800000000
-
 #define CONFIG_SYS_DDR_CS0_BNDS                0x0000003F
 #define CONFIG_SYS_DDR_CS0_CONFIG      0x80014202
 #define CONFIG_SYS_DDR_CS0_CONFIG_2    0x00000000
@@ -76,19 +68,19 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 #define CONFIG_SYS_DDR_TIMING_0_667    0x55770802
 #define CONFIG_SYS_DDR_TIMING_1_667    0x5f599543
 #define CONFIG_SYS_DDR_TIMING_2_667    0x0fa074d1
-#define CONFIG_SYS_DDR_CLK_CTRL_667    0x02800000
+#define CONFIG_SYS_DDR_CLK_CTRL_667    0x03000000
 #define CONFIG_SYS_DDR_MODE_1_667      0x00040852
 #define CONFIG_SYS_DDR_MODE_2_667      0x00000000
 #define CONFIG_SYS_DDR_INTERVAL_667    0x0a280100
 
 #define CONFIG_SYS_DDR_TIMING_3_800    0x00040000
-#define CONFIG_SYS_DDR_TIMING_0_800    0x55770802
+#define CONFIG_SYS_DDR_TIMING_0_800    0x00770802
 #define CONFIG_SYS_DDR_TIMING_1_800    0x6f6b6543
 #define CONFIG_SYS_DDR_TIMING_2_800    0x0fa074d1
-#define CONFIG_SYS_DDR_CLK_CTRL_800    0x02000000
-#define CONFIG_SYS_DDR_MODE_1_800      0x00440862
+#define CONFIG_SYS_DDR_CLK_CTRL_800    0x02800000
+#define CONFIG_SYS_DDR_MODE_1_800      0x00040852
 #define CONFIG_SYS_DDR_MODE_2_800      0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_800    0x0a280100
+#define CONFIG_SYS_DDR_INTERVAL_800    0x0c300100
 
 fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
        .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
@@ -204,54 +196,48 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
 
 phys_size_t fixed_sdram (void)
 {
-       sys_info_t sysinfo;
        char buf[32];
-       fsl_ddr_cfg_regs_t *ddr_cfg_regs = NULL;
+       fsl_ddr_cfg_regs_t ddr_cfg_regs;
        size_t ddr_size;
        struct cpu_type *cpu;
+       ulong ddr_freq, ddr_freq_mhz;
 
-       get_sys_info(&sysinfo);
-       printf("Configuring DDR for %s MT/s data rate\n",
-                               strmhz(buf, sysinfo.freqDDRBus));
+       cpu = gd->arch.cpu;
+       /* P1020 and it's derivatives support max 32bit DDR width */
+       if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
+               ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
+       } else {
+               ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+       }
+#if defined(CONFIG_SYS_RAMBOOT)
+       return ddr_size;
+#endif
+       ddr_freq = get_ddr_freq(0);
+       ddr_freq_mhz = ddr_freq / 1000000;
 
-       if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
-               ddr_cfg_regs = &ddr_cfg_regs_400;
-       else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
-               ddr_cfg_regs = &ddr_cfg_regs_533;
-       else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
-               ddr_cfg_regs = &ddr_cfg_regs_667;
-       else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
-               ddr_cfg_regs = &ddr_cfg_regs_800;
+       printf("Configuring DDR for %s MT/s data rate\n",
+                               strmhz(buf, ddr_freq));
+
+       if(ddr_freq_mhz <= 400)
+               memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
+       else if(ddr_freq_mhz <= 533)
+               memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
+       else if(ddr_freq_mhz <= 667)
+               memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
+       else if(ddr_freq_mhz <= 800)
+               memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
        else
                panic("Unsupported DDR data rate %s MT/s data rate\n",
-                                       strmhz(buf, sysinfo.freqDDRBus));
+                                       strmhz(buf, ddr_freq));
 
-       cpu = gd->cpu;
        /* P1020 and it's derivatives support max 32bit DDR width */
-       if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
-               cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
-               ddr_cfg_regs->ddr_sdram_cfg |= SDRAM_CFG_32_BE;
-               ddr_cfg_regs->cs[0].bnds = 0x0000001F;
-               ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
+       if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
+               ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
+               ddr_cfg_regs.cs[0].bnds = 0x0000001F;
        }
-       else
-               ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 
-       fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0);
+       fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
 
+       set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
        return ddr_size;
 }
-
-phys_size_t initdram(int board_type)
-{
-       phys_size_t dram_size = 0;
-
-       dram_size = fixed_sdram();
-       set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);
-
-       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-       dram_size *= 0x100000;
-
-       puts("DDR: ");
-       return dram_size;
-}