Merge branch 'master' of git://git.denx.de/u-boot-x86

[karo-tx-uboot.git] / board / freescale / p1_p2_rdb / ddr.c

diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index fbc46b1f4b09c4e98ad90ad3ccffa56f9d3b6df0..b16b8c8a902afd319e45fa9ca93b910ff7c4c4ef 100644 (file)
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -30,9 +30,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-                                  unsigned int ctrl_num);
-
 #define CONFIG_SYS_DDR_CS0_BNDS                0x0000003F
 #define CONFIG_SYS_DDR_CS0_CONFIG      0x80014202
 #define CONFIG_SYS_DDR_CS0_CONFIG_2    0x00000000
@@ -77,13 +74,13 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 #define CONFIG_SYS_DDR_INTERVAL_667    0x0a280100
 
 #define CONFIG_SYS_DDR_TIMING_3_800    0x00040000
-#define CONFIG_SYS_DDR_TIMING_0_800    0x55770802
+#define CONFIG_SYS_DDR_TIMING_0_800    0x00770802
 #define CONFIG_SYS_DDR_TIMING_1_800    0x6f6b6543
 #define CONFIG_SYS_DDR_TIMING_2_800    0x0fa074d1
 #define CONFIG_SYS_DDR_CLK_CTRL_800    0x02800000
 #define CONFIG_SYS_DDR_MODE_1_800      0x00040852
 #define CONFIG_SYS_DDR_MODE_2_800      0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_800    0x0a280100
+#define CONFIG_SYS_DDR_INTERVAL_800    0x0c300100
 
 fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
        .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
@@ -205,6 +202,16 @@ phys_size_t fixed_sdram (void)
        struct cpu_type *cpu;
        ulong ddr_freq, ddr_freq_mhz;
 
+       cpu = gd->arch.cpu;
+       /* P1020 and it's derivatives support max 32bit DDR width */
+       if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
+               ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
+       } else {
+               ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+       }
+#if defined(CONFIG_SYS_RAMBOOT)
+       return ddr_size;
+#endif
        ddr_freq = get_ddr_freq(0);
        ddr_freq_mhz = ddr_freq / 1000000;
 
@@ -223,16 +230,11 @@ phys_size_t fixed_sdram (void)
                panic("Unsupported DDR data rate %s MT/s data rate\n",
                                        strmhz(buf, ddr_freq));
 
-       cpu = gd->cpu;
        /* P1020 and it's derivatives support max 32bit DDR width */
-       if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
-               cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
+       if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
                ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
                ddr_cfg_regs.cs[0].bnds = 0x0000001F;
-               ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
        }
-       else
-               ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 
        fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);