Merge branch 'master' of /home/wd/git/u-boot/master

[karo-tx-uboot.git] / board / freescale / p2020ds / p2020ds.c

diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index f0ff209c0c28764a1906e02ba2a71b9fb656ec58..608ff916da819f78236bed570c8572ba30bfd525 100644 (file)
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -69,13 +69,16 @@ int checkboard(void)
        return 0;
 }
 
+const char *board_hwconfig = "foo:bar=baz";
+const char *cpu_hwconfig = "foo:bar=baz";
+
 phys_size_t initdram(int board_type)
 {
        phys_size_t dram_size = 0;
 
        puts("Initializing....");
 
-#ifdef CONFIG_SPD_EEPROM
+#ifdef CONFIG_DDR_SPD
        dram_size = fsl_ddr_sdram();
 #else
        dram_size = fixed_sdram();
@@ -94,7 +97,7 @@ phys_size_t initdram(int board_type)
        return dram_size;
 }
 
-#if !defined(CONFIG_SPD_EEPROM)
+#if !defined(CONFIG_DDR_SPD)
 /*
  * Fixed sdram init -- doesn't use serial presence detect.
  */
@@ -313,155 +316,6 @@ int board_early_init_r(void)
        return 0;
 }
 
-#ifdef CONFIG_GET_CLK_FROM_ICS307
-/* decode S[0-2] to Output Divider (OD) */
-static unsigned char ics307_S_to_OD[] = {
-       10, 2, 8, 4, 5, 7, 3, 6
-};
-
-/* Calculate frequency being generated by ICS307-02 clock chip based upon
- * the control bytes being programmed into it. */
-/* XXX: This function should probably go into a common library */
-static unsigned long
-ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
-{
-       const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
-       unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
-       unsigned long RDW = cw2 & 0x7F;
-       unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
-       unsigned long freq;
-
-       /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
-
-       /* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
-        * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
-        * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
-        *
-        * R6:R0 = Reference Divider Word (RDW)
-        * V8:V0 = VCO Divider Word (VDW)
-        * S2:S0 = Output Divider Select (OD)
-        * F1:F0 = Function of CLK2 Output
-        * TTL = duty cycle
-        * C1:C0 = internal load capacitance for cyrstal
-        */
-
-       /* Adding 1 to get a "nicely" rounded number, but this needs
-        * more tweaking to get a "properly" rounded number. */
-
-       freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
-
-       debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
-                       freq);
-       return freq;
-}
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
-       return gd->bus_clk;
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
-       return gd->mem_clk;
-}
-
-unsigned long calculate_board_sys_clk(ulong dummy)
-{
-       ulong val;
-
-       val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]),
-                             in_8(&pixis->sclk[2]));
-       debug("sysclk val = %lu\n", val);
-       return val;
-}
-
-unsigned long calculate_board_ddr_clk(ulong dummy)
-{
-       ulong val;
-
-       val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]),
-                             in_8(&pixis->dclk[2]));
-       debug("ddrclk val = %lu\n", val);
-       return val;
-}
-#else
-unsigned long get_board_sys_clk(ulong dummy)
-{
-       u8 i;
-       ulong val = 0;
-
-       i = in_8(&pixis->spd);
-       i &= 0x07;
-
-       switch (i) {
-               case 0:
-                       val = 33333333;
-                       break;
-               case 1:
-                       val = 40000000;
-                       break;
-               case 2:
-                       val = 50000000;
-                       break;
-               case 3:
-                       val = 66666666;
-                       break;
-               case 4:
-                       val = 83333333;
-                       break;
-               case 5:
-                       val = 100000000;
-                       break;
-               case 6:
-                       val = 133333333;
-                       break;
-               case 7:
-                       val = 166666666;
-                       break;
-       }
-
-       return val;
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
-       u8 i;
-       ulong val = 0;
-
-       i = in_8(&pixis->spd);
-       i &= 0x38;
-       i >>= 3;
-
-       switch (i) {
-               case 0:
-                       val = 33333333;
-                       break;
-               case 1:
-                       val = 40000000;
-                       break;
-               case 2:
-                       val = 50000000;
-                       break;
-               case 3:
-                       val = 66666666;
-                       break;
-               case 4:
-                       val = 83333333;
-                       break;
-               case 5:
-                       val = 100000000;
-                       break;
-               case 6:
-                       val = 133333333;
-                       break;
-               case 7:
-                       val = 166666666;
-                       break;
-       }
-       return val;
-}
-#endif
-
 #ifdef CONFIG_TSEC_ENET
 int board_eth_init(bd_t *bis)
 {
@@ -515,15 +369,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 
        fdt_fixup_memory(blob, (u64)base, (u64)size);
 
-#ifdef CONFIG_PCIE3
-       ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
-#endif
-#ifdef CONFIG_PCIE2
-       ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#endif
-#ifdef CONFIG_PCIE1
-       ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#endif
+       FT_FSL_PCI_SETUP;
+
 #ifdef CONFIG_FSL_SGMII_RISER
        fsl_sgmii_riser_fdt_fixup(blob);
 #endif