/*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011,2012 Freescale Semiconductor, Inc.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
extern void pci_of_setup(void *blob, bd_t *bd);
int checkboard(void)
{
u8 sw;
- struct cpu_type *cpu = gd->cpu;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ struct cpu_type *cpu = gd->arch.cpu;
unsigned int i;
printf("Board: %sRDB, ", cpu->name);
sw = CPLD_READ(fbank_sel);
printf("vBank: %d\n", sw & 0x1);
-#ifdef CONFIG_PHYS_64BIT
- puts("36-bit Addressing\n");
-#endif
-
- /*
- * Display the RCW, so that no one gets confused as to what RCW
- * we're actually using for this boot.
- */
- puts("Reset Configuration Word (RCW):");
- for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
- u32 rcw = in_be32(&gur->rcwsr[i]);
-
- if ((i % 4) == 0)
- printf("\n %08x:", i * 4);
- printf(" %08x", rcw);
- }
- puts("\n");
-
/*
* Display the actual SERDES reference clocks as configured by the
* dip switches on the board. Note that the SWx registers could
puts("SERDES Reference Clocks: ");
sw = in_8(&CPLD_SW(2)) >> 2;
for (i = 0; i < 2; i++) {
- static const char * const freq[] = {"0", "100", "125"};
+ static const char * const freq[][3] = {{"0", "100", "125"},
+ {"100", "156.25", "125"}
+ };
unsigned int clock = (sw >> (2 * i)) & 3;
- printf("Bank%u=%sMhz ", i+1, freq[clock]);
+ printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
}
puts("\n");
return 0;
}
+#define CPLD_LANE_A_SEL 0x1
+#define CPLD_LANE_G_SEL 0x2
+#define CPLD_LANE_C_SEL 0x4
+#define CPLD_LANE_D_SEL 0x8
+
+void board_config_lanes_mux(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+ u8 mux = 0;
+ switch (srds_prtcl) {
+ case 0x2:
+ case 0x5:
+ case 0x9:
+ case 0xa:
+ case 0xf:
+ break;
+ case 0x8:
+ mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+ break;
+ case 0x14:
+ mux |= CPLD_LANE_A_SEL;
+ break;
+ case 0x17:
+ mux |= CPLD_LANE_G_SEL;
+ break;
+ case 0x16:
+ case 0x19:
+ case 0x1a:
+ mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+ break;
+ case 0x1c:
+ mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
+ break;
+ default:
+ printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
+ break;
+ }
+ CPLD_WRITE(serdes_mux, mux);
+}
+
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
flush_dcache();
invalidate_icache();
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
set_liodns();
setup_portals();
+ board_config_lanes_mux();
return 0;
}
-static const char *serdes_clock_to_string(u32 clock)
+unsigned long get_board_sys_clk(unsigned long dummy)
{
- switch (clock) {
- case SRDS_PLLCR0_RFCK_SEL_100:
- return "100";
- case SRDS_PLLCR0_RFCK_SEL_125:
- return "125";
- case SRDS_PLLCR0_RFCK_SEL_156_25:
- return "156.25";
+ u8 sysclk_conf = CPLD_READ(sysclk_sw1);
+
+ switch (sysclk_conf & 0x7) {
+ case CPLD_SYSCLK_83:
+ return 83333333;
+ case CPLD_SYSCLK_100:
+ return 100000000;
default:
- return "150";
+ return 66666666;
}
}
u32 actual[NUM_SRDS_BANKS];
unsigned int i;
u8 sw;
+ static const int freq[][3] = {
+ {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
+ {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
+ SRDS_PLLCR0_RFCK_SEL_125}
+ };
sw = in_8(&CPLD_SW(2)) >> 2;
for (i = 0; i < NUM_SRDS_BANKS; i++) {
unsigned int clock = (sw >> (2 * i)) & 3;
- switch (clock) {
- case 1:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
- break;
- case 2:
- actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
- break;
- default:
+ if (clock == 0x3) {
printf("Warning: SDREFCLK%u switch setting of '11' is "
"unsupported\n", i + 1);
break;
}
+ if (i == 0 && clock == 0)
+ puts("Warning: SDREFCLK1 switch setting of"
+ "'00' is unsupported\n");
+ else
+ actual[i] = freq[i][clock];
+
+ /*
+ * PC board uses a different CPLD with PB board, this CPLD
+ * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
+ * board has cpld_ver_sub = 0, and pcba_ver = 4.
+ */
+ if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
+ (CPLD_READ(pcba_ver) == 5)) {
+ /* PC board bank2 frequency */
+ actual[i] = freq[i-1][clock];
+ }
}
for (i = 0; i < NUM_SRDS_BANKS; i++) {
fdt_fixup_memory(blob, (u64)base, (u64)size);
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
#ifdef CONFIG_PCI
pci_of_setup(blob, bd);
#endif
fdt_fixup_liodn(blob);
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+#endif
}
projects / karo-tx-uboot.git / blobdiff