#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(cpld_base + 0x17, 0x40);
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- puts(" DDR: ");
+#else
+ dram_size = fsl_ddr_sdram_size();
+#endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}