Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / board / freescale / t4qds / ddr.c

diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 692616aed4d88f0f58a65f6a14ceef9c178bd203..7586cc3c4bda640e0e07ee786fdd6490bee8e2e4 100644 (file)
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -10,80 +10,13 @@
 #include <i2c.h>
 #include <hwconfig.h>
 #include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
+#include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct board_specific_parameters {
-       u32 n_ranks;
-       u32 datarate_mhz_high;
-       u32 clk_adjust;
-       u32 wrlvl_start;
-       u32 wrlvl_ctl_2;
-       u32 wrlvl_ctl_3;
-       u32 cpo;
-       u32 write_data_delay;
-       u32 force_2T;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
-       /*
-        * memory controller 0
-        *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-        * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
-        */
-       {2,  1350,    5,     7, 0x0809090b, 0x0c0c0d09,   0xff,    2,  0},
-       {2,  1666,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-       {2,  2140,    5,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
-       {1,  1350,    5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-       {1,  1700,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-       {1,  1900,    4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-       {1,  2140,    4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
-       {}
-};
-
-/*
- * The three slots have slightly different timing. The center values are good
- * for all slots. We use identical speed tables for them. In future use, if
- * DIMMs require separated tables, make more entries as needed.
- */
-static const struct board_specific_parameters *udimms[] = {
-       udimm0,
-};
-
-static const struct board_specific_parameters rdimm0[] = {
-       /*
-        * memory controller 0
-        *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-        * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
-        */
-       {4,  1350,    5,     9, 0x08070605, 0x07080805,   0xff,    2,  0},
-       {4,  1666,    5,     8, 0x08070605, 0x07080805,   0xff,    2,  0},
-       {4,  2140,    5,     8, 0x08070605, 0x07081805,   0xff,    2,  0},
-       {2,  1350,    5,     7, 0x0809090b, 0x0c0c0d09,   0xff,    2,  0},
-       {2,  1666,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-       {2,  2140,    5,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
-       {1,  1350,    5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-       {1,  1700,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-       {1,  1900,    4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-       {1,  2140,    4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
-       {}
-};
-
-/*
- * The three slots have slightly different timing. See comments above.
- */
-static const struct board_specific_parameters *rdimms[] = {
-       rdimm0,
-};
-
 void fsl_ddr_board_options(memctl_options_t *popts,
                                dimm_params_t *pdimm,
                                unsigned int ctrl_num)
@@ -113,7 +46,8 @@ void fsl_ddr_board_options(memctl_options_t *popts,
         */
        ddr_freq = get_ddr_freq(0) / 1000000;
        while (pbsp->datarate_mhz_high) {
-               if (pbsp->n_ranks == pdimm->n_ranks) {
+               if (pbsp->n_ranks == pdimm->n_ranks &&
+                   (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
                        if (ddr_freq <= pbsp->datarate_mhz_high) {
                                popts->cpo_override = pbsp->cpo;
                                popts->write_data_delay =
@@ -122,7 +56,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                                popts->wrlvl_start = pbsp->wrlvl_start;
                                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
                                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-                               popts->twoT_en = pbsp->force_2T;
+                               popts->twot_en = pbsp->force_2t;
                                goto found;
                        }
                        pbsp_highest = pbsp;
@@ -141,11 +75,18 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                popts->wrlvl_start = pbsp_highest->wrlvl_start;
                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-               popts->twoT_en = pbsp_highest->force_2T;
+               popts->twot_en = pbsp_highest->force_2t;
        } else {
                panic("DIMM is not supported by this board");
        }
 found:
+       debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+               "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+               "wrlvl_ctrl_3 0x%x\n",
+               pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+               pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+               pbsp->wrlvl_ctl_3);
+
        /*
         * Factors to consider for half-strength driver enable:
         *      - number of DIMMs installed