powerpc/t4240qds: fix PHY reset timeout issue

[karo-tx-uboot.git] / board / freescale / t4qds / eth.c

diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index 2232eea49bf7ea9adb0419df9a55e9c9ee9177da..7103a0d38d477c3d293633be999b50034fb0a59e 100644 (file)
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -78,6 +78,7 @@ static u8 slot_qsgmii_phyaddr[5][4] = {
        {8, 9, 0xa, 0xb},
        {0xc, 0xd, 0xe, 0xf},
 };
+static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
 
 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
 {
@@ -189,17 +190,87 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
 {
        if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
                switch (port) {
+               case FM1_DTSEC1:
+                       if (qsgmiiphy_fix[port])
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "sgmii_phy21");
+                       break;
+               case FM1_DTSEC2:
+                       if (qsgmiiphy_fix[port])
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "sgmii_phy22");
+                       break;
+               case FM1_DTSEC3:
+                       if (qsgmiiphy_fix[port])
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "sgmii_phy23");
+                       break;
+               case FM1_DTSEC4:
+                       if (qsgmiiphy_fix[port])
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "sgmii_phy24");
+                       break;
+               case FM1_DTSEC6:
+                       if (qsgmiiphy_fix[port])
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "sgmii_phy12");
+                       break;
                case FM1_DTSEC9:
-                       fdt_set_phy_handle(blob, prop, pa, "phy_sgmii4");
+                       if (qsgmiiphy_fix[port])
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "sgmii_phy14");
+                       else
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "phy_sgmii4");
                        break;
                case FM1_DTSEC10:
-                       fdt_set_phy_handle(blob, prop, pa, "phy_sgmii3");
+                       if (qsgmiiphy_fix[port])
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "sgmii_phy13");
+                       else
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "phy_sgmii3");
+                       break;
+               case FM2_DTSEC1:
+                       if (qsgmiiphy_fix[port])
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "sgmii_phy41");
+                       break;
+               case FM2_DTSEC2:
+                       if (qsgmiiphy_fix[port])
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "sgmii_phy42");
+                       break;
+               case FM2_DTSEC3:
+                       if (qsgmiiphy_fix[port])
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "sgmii_phy43");
+                       break;
+               case FM2_DTSEC4:
+                       if (qsgmiiphy_fix[port])
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "sgmii_phy44");
+                       break;
+               case FM2_DTSEC6:
+                       if (qsgmiiphy_fix[port])
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "sgmii_phy32");
                        break;
                case FM2_DTSEC9:
-                       fdt_set_phy_handle(blob, prop, pa, "phy_sgmii12");
+                       if (qsgmiiphy_fix[port])
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "sgmii_phy34");
+                       else
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "phy_sgmii12");
                        break;
                case FM2_DTSEC10:
-                       fdt_set_phy_handle(blob, prop, pa, "phy_sgmii11");
+                       if (qsgmiiphy_fix[port])
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "sgmii_phy33");
+                       else
+                               fdt_set_phy_handle(blob, prop, pa,
+                                                  "phy_sgmii11");
                        break;
                default:
                        break;
@@ -263,6 +334,78 @@ void fdt_fixup_board_enet(void *fdt)
        }
 }
 
+static void initialize_qsgmiiphy_fix(void)
+{
+       int i;
+       unsigned short reg;
+
+       for (i = 1; i <= 4; i++) {
+               /*
+                * Try to read if a SGMII card is used, we do it slot by slot.
+                * if a SGMII PHY address is valid on a slot, then we mark
+                * all ports on the slot, then fix the PHY address for the
+                * marked port when doing dtb fixup.
+                */
+               if (miiphy_read(mdio_names[i],
+                               SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, &reg) != 0) {
+                       debug("Slot%d PHY ID register 2 read failed\n", i);
+                       continue;
+               }
+
+               debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
+
+               if (reg == 0xFFFF) {
+                       /* No physical device present at this address */
+                       continue;
+               }
+
+               switch (i) {
+               case 1:
+                       qsgmiiphy_fix[FM1_DTSEC5] = 1;
+                       qsgmiiphy_fix[FM1_DTSEC6] = 1;
+                       qsgmiiphy_fix[FM1_DTSEC9] = 1;
+                       qsgmiiphy_fix[FM1_DTSEC10] = 1;
+                       slot_qsgmii_phyaddr[1][0] =  SGMII_CARD_PORT1_PHY_ADDR;
+                       slot_qsgmii_phyaddr[1][1] =  SGMII_CARD_PORT2_PHY_ADDR;
+                       slot_qsgmii_phyaddr[1][2] =  SGMII_CARD_PORT3_PHY_ADDR;
+                       slot_qsgmii_phyaddr[1][3] =  SGMII_CARD_PORT4_PHY_ADDR;
+                       break;
+               case 2:
+                       qsgmiiphy_fix[FM1_DTSEC1] = 1;
+                       qsgmiiphy_fix[FM1_DTSEC2] = 1;
+                       qsgmiiphy_fix[FM1_DTSEC3] = 1;
+                       qsgmiiphy_fix[FM1_DTSEC4] = 1;
+                       slot_qsgmii_phyaddr[2][0] =  SGMII_CARD_PORT1_PHY_ADDR;
+                       slot_qsgmii_phyaddr[2][1] =  SGMII_CARD_PORT2_PHY_ADDR;
+                       slot_qsgmii_phyaddr[2][2] =  SGMII_CARD_PORT3_PHY_ADDR;
+                       slot_qsgmii_phyaddr[2][3] =  SGMII_CARD_PORT4_PHY_ADDR;
+                       break;
+               case 3:
+                       qsgmiiphy_fix[FM2_DTSEC5] = 1;
+                       qsgmiiphy_fix[FM2_DTSEC6] = 1;
+                       qsgmiiphy_fix[FM2_DTSEC9] = 1;
+                       qsgmiiphy_fix[FM2_DTSEC10] = 1;
+                       slot_qsgmii_phyaddr[3][0] =  SGMII_CARD_PORT1_PHY_ADDR;
+                       slot_qsgmii_phyaddr[3][1] =  SGMII_CARD_PORT2_PHY_ADDR;
+                       slot_qsgmii_phyaddr[3][2] =  SGMII_CARD_PORT3_PHY_ADDR;
+                       slot_qsgmii_phyaddr[3][3] =  SGMII_CARD_PORT4_PHY_ADDR;
+                       break;
+               case 4:
+                       qsgmiiphy_fix[FM2_DTSEC1] = 1;
+                       qsgmiiphy_fix[FM2_DTSEC2] = 1;
+                       qsgmiiphy_fix[FM2_DTSEC3] = 1;
+                       qsgmiiphy_fix[FM2_DTSEC4] = 1;
+                       slot_qsgmii_phyaddr[4][0] =  SGMII_CARD_PORT1_PHY_ADDR;
+                       slot_qsgmii_phyaddr[4][1] =  SGMII_CARD_PORT2_PHY_ADDR;
+                       slot_qsgmii_phyaddr[4][2] =  SGMII_CARD_PORT3_PHY_ADDR;
+                       slot_qsgmii_phyaddr[4][3] =  SGMII_CARD_PORT4_PHY_ADDR;
+                       break;
+               default:
+                       break;
+               }
+       }
+}
+
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FMAN_ENET)
@@ -308,6 +451,7 @@ int board_eth_init(bd_t *bis)
        t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
        t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 
+       initialize_qsgmiiphy_fix();
 
        switch (srds_prtcl_s1) {
        case 1: