0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
/* exception (offset 0x3C in upm ram) */
- };
+};
const uint selectmap_upm_table[] = {
/* single read (offset 0x00 in upm ram) */
/*
* Check board identity. Always successful (gives information only)
*/
-int
-checkboard(void)
+int checkboard (void)
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned char *s;
- unsigned char buf[64];
- int i;
+ unsigned char *s;
+ unsigned char buf[64];
+ int i;
- i = getenv_r("board_id", buf, sizeof(buf));
- s = (i>0) ? buf : NULL;
+ i = getenv_r ("board_id", buf, sizeof (buf));
+ s = (i > 0) ? buf : NULL;
if (s) {
- printf("%s ", s);
+ printf ("%s ", s);
} else {
- printf("<unknown> ");
+ printf ("<unknown> ");
}
- i = getenv_r("serial#", buf, sizeof(buf));
- s = (i>0) ? buf : NULL;
+ i = getenv_r ("serial#", buf, sizeof (buf));
+ s = (i > 0) ? buf : NULL;
if (s) {
- printf("S/N %s\n", s);
+ printf ("S/N %s\n", s);
} else {
- printf("S/N <unknown>\n");
+ printf ("S/N <unknown>\n");
}
- printf("CPU at %s MHz, ",strmhz(buf, gd->cpu_clk));
- printf("local bus at %s MHz\n", strmhz(buf, gd->bus_clk));
- return (0);
+ printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));
+ printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk));
+ return (0);
}
/*
* Initialize SDRAM
*/
-long int
-initdram(int board_type)
+long int initdram (int board_type)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
-
- upmconfig(UPMA,
- (uint *)sdram_upm_table,
- sizeof(sdram_upm_table) / sizeof(uint)
- );
-
- /*
- * Setup MAMR register
- */
- memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
- memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- /*
- * Map CS1* to SDRAM bank
- */
- memctl->memc_or1 = CFG_OR1;
- memctl->memc_br1 = CFG_BR1;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
+
+ upmconfig (UPMA,
+ (uint *) sdram_upm_table,
+ sizeof (sdram_upm_table) / sizeof (uint)
+ );
+
+ /*
+ * Setup MAMR register
+ */
+ memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+ memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+
+ /*
+ * Map CS1* to SDRAM bank
+ */
+ memctl->memc_or1 = CFG_OR1;
+ memctl->memc_br1 = CFG_BR1;
/*
* Perform SDRAM initialization sequence:
* Program SDRAM for standard operation, sequential burst, burst length
* of 4, CAS latency of 2.
*/
- memctl->memc_mar = 0x00000000;
+ memctl->memc_mar = 0x00000000;
memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
- MCR_MLCF(0) | UPMA_NOP_ADDR;
- udelay(200);
- memctl->memc_mar = 0x00000000;
+ MCR_MLCF (0) | UPMA_NOP_ADDR;
+ udelay (200);
+ memctl->memc_mar = 0x00000000;
memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
- MCR_MLCF(4) | UPMA_PRECHARGE_ADDR;
+ MCR_MLCF (4) | UPMA_PRECHARGE_ADDR;
- memctl->memc_mar = 0x00000000;
+ memctl->memc_mar = 0x00000000;
memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
- MCR_MLCF(2) | UPM_REFRESH_ADDR;
+ MCR_MLCF (2) | UPM_REFRESH_ADDR;
- memctl->memc_mar = 0x00000088;
+ memctl->memc_mar = 0x00000088;
memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
- MCR_MLCF(1) | UPMA_MRS_ADDR;
+ MCR_MLCF (1) | UPMA_MRS_ADDR;
- memctl->memc_mar = 0x00000000;
+ memctl->memc_mar = 0x00000000;
memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
- MCR_MLCF(0) | UPMA_NOP_ADDR;
+ MCR_MLCF (0) | UPMA_NOP_ADDR;
/*
* Enable refresh
*/
- memctl->memc_mamr |= MAMR_PTAE;
+ memctl->memc_mamr |= MAMR_PTAE;
- return (SDRAM_SIZE);
+ return (SDRAM_SIZE);
}
/*
* The DOC lives in the CS2* space
*/
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
-extern void
-doc_probe(ulong physadr);
+extern void doc_probe (ulong physadr);
-void
-doc_init(void)
+void doc_init (void)
{
- printf("Probing at 0x%.8x: ", DOC_BASE);
- doc_probe(DOC_BASE);
+ printf ("Probing at 0x%.8x: ", DOC_BASE);
+ doc_probe (DOC_BASE);
}
#endif
/*
* Miscellaneous intialization
*/
-int
-misc_init_r (void)
+int misc_init_r (void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
/*
* Set up UPMB to handle the Virtex FPGA SelectMap interface
*/
- upmconfig(UPMB, (uint *)selectmap_upm_table,
- sizeof(selectmap_upm_table) / sizeof(uint));
+ upmconfig (UPMB, (uint *) selectmap_upm_table,
+ sizeof (selectmap_upm_table) / sizeof (uint));
- memctl->memc_mbmr = 0x0;
+ memctl->memc_mbmr = 0x0;
- config_mpc8xx_ioports(immr);
+ config_mpc8xx_ioports (immr);
#if (CONFIG_COMMANDS & CFG_CMD_MII)
- mii_init();
+ mii_init ();
#endif
#if (CONFIG_FPGA)
- gen860t_init_fpga();
+ gen860t_init_fpga ();
#endif
return 0;
}
/*
* Final init hook before entering command loop.
*/
-int
-last_stage_init(void)
+int last_stage_init (void)
{
#if !defined(CONFIG_SC)
unsigned char buf[256];
/*
* Turn the beeper volume all the way down in case this is a warm boot.
*/
- set_beeper_volume(-64);
- init_beeper();
+ set_beeper_volume (-64);
+ init_beeper ();
/*
* Read the environment to see what to do with the beeper
*/
- i = getenv_r("beeper", buf, sizeof(buf));
+ i = getenv_r ("beeper", buf, sizeof (buf));
if (i > 0) {
- do_beeper(buf);
+ do_beeper (buf);
}
#endif
return 0;
/*
* Stub to make POST code happy. Can't self-poweroff, so just hang.
*/
-void
-board_poweroff(void)
+void board_poweroff (void)
{
- puts("### Please power off the board ###\n");
- while (1);
+ puts ("### Please power off the board ###\n");
+ while (1);
}
#ifdef CONFIG_POST
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
-int post_hotkeys_pressed(void)
+int post_hotkeys_pressed (void)
{
- return 0; /* No hotkeys supported */
+ return 0; /* No hotkeys supported */
}
#endif
projects / karo-tx-uboot.git / blobdiff