Merge git://git.denx.de/u-boot-arm

[karo-tx-uboot.git] / board / jse / sdram.c

diff --git a/board/jse/sdram.c b/board/jse/sdram.c
index bb6f85eee51b56c5492b0eee898910eb52082efc..5639beddce9f6299b68a3ae4c67a692fa64d35ba 100644 (file)
--- a/board/jse/sdram.c
+++ b/board/jse/sdram.c
@@ -2,24 +2,11 @@
  * Copyright (c) 2004 Picture Elements, Inc.
  *    Stephen Williams (steve@icarus.com)
  *
- *    This source code is free software; you can redistribute it
- *    and/or modify it in source code form under the terms of the GNU
- *    General Public License as published by the Free Software
- *    Foundation; either version 2 of the License, or (at your option)
- *    any later version.
- *
- *    This program is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <asm/processor.h>
 
 # define SDRAM_LEN 0x08000000
@@ -27,7 +14,7 @@
 /*
  * this is even after checkboard. It returns the size of the SDRAM
  * that we have installed. This function is called by board_init_f
- * in lib_ppc/board.c to initialize the memory and return what I
+ * in arch/powerpc/lib/board.c to initialize the memory and return what I
  * found.
  */
 phys_size_t initdram (int board_type)
@@ -35,59 +22,59 @@ phys_size_t initdram (int board_type)
        /* Configure the SDRAMS */
 
        /* disable memory controller */
-       mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
        mtdcr (SDRAM0_CFGDATA, 0x00000000);
 
        udelay (500);
 
        /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
-       mtdcr (SDRAM0_CFGADDR, mem_besra);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0);
        mtdcr (SDRAM0_CFGDATA, 0xffffffff);
 
        /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
-       mtdcr (SDRAM0_CFGADDR, mem_besrb);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1);
        mtdcr (SDRAM0_CFGDATA, 0xffffffff);
 
        /* Clear SDRAM0_ECCCFG (disable ECC) */
-       mtdcr (SDRAM0_CFGADDR, mem_ecccf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
        mtdcr (SDRAM0_CFGDATA, 0x00000000);
 
        /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
-       mtdcr (SDRAM0_CFGADDR, mem_eccerr);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR);
        mtdcr (SDRAM0_CFGDATA, 0xffffffff);
 
        /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
-       mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
        mtdcr (SDRAM0_CFGDATA, 0x010a4016);
 
        /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
-       mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
        mtdcr (SDRAM0_CFGDATA, 0x00084001);
 
        /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
-       mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
        mtdcr (SDRAM0_CFGDATA, 0x04084001);
 
        /* Memory Bank 2 Config ==  BE=0 */
-       mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
        mtdcr (SDRAM0_CFGDATA, 0x00000000);
 
        /* Memory Bank 3 Config ==  BE=0 */
-       mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
        mtdcr (SDRAM0_CFGDATA, 0x00000000);
 
        /* refresh timer = 0x400  */
-       mtdcr (SDRAM0_CFGADDR, mem_rtr);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
        mtdcr (SDRAM0_CFGDATA, 0x04000000);
 
        /* Power management idle timer set to the default. */
-       mtdcr (SDRAM0_CFGADDR, mem_pmit);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT);
        mtdcr (SDRAM0_CFGDATA, 0x07c00000);
 
        udelay (500);
 
        /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
-       mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
        mtdcr (SDRAM0_CFGDATA, 0x80e00000);
 
        return SDRAM_LEN;
@@ -108,7 +95,7 @@ int testdram (void)
 #ifdef DEBUG
        printf ("SDRAM Controller Registers --\n");
 
-       mtdcr (SDRAM0_CFGADDR, mem_mcopt1);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
        val = mfdcr (SDRAM0_CFGDATA);
        printf ("    SDRAM0_CFG   : 0x%08x\n", val);
 
@@ -116,19 +103,19 @@ int testdram (void)
        val = mfdcr (SDRAM0_CFGDATA);
        printf ("    SDRAM0_STATUS: 0x%08x\n", val);
 
-       mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
        val = mfdcr (SDRAM0_CFGDATA);
        printf ("    SDRAM0_B0CR  : 0x%08x\n", val);
 
-       mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
        val = mfdcr (SDRAM0_CFGDATA);
        printf ("    SDRAM0_B1CR  : 0x%08x\n", val);
 
-       mtdcr (SDRAM0_CFGADDR, mem_sdtr1);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
        val = mfdcr (SDRAM0_CFGDATA);
        printf ("    SDRAM0_TR    : 0x%08x\n", val);
 
-       mtdcr (SDRAM0_CFGADDR, mem_rtr);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
        val = mfdcr (SDRAM0_CFGDATA);
        printf ("    SDRAM0_RTR   : 0x%08x\n", val);
 #endif