/*
- * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
- * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
*/
#include <common.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <video_fb.h>
-#include <ipu_pixfmt.h>
-#include <mx2fb.h>
+#include <ipu.h>
+#include <mxcfb.h>
#include <linux/fb.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include "../common/karo.h"
-#define IMX_GPIO_NR(b, o) ((((b) - 1) << 5) | (o))
-
#define TX53_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
#define TX53_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
#define TX53_FEC_INT_GPIO IMX_GPIO_NR(2, 4)
DECLARE_GLOBAL_DATA_PTR;
-#define MX53_GPIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+#define MX53_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
-#define TX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
- PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN)
+#define TX53_SDHC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
static iomux_v3_cfg_t tx53_pads[] = {
/* NAND flash pads are set up in lowlevel_init.S */
- /* RESET_OUT */
- MX53_PAD_GPIO_17__GPIO7_12,
-
/* UART pads */
#if CONFIG_MXC_UART_BASE == UART1_BASE
MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
MX53_PAD_PATA_DA_1__UART3_CTS,
#endif
/* internal I2C */
- NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, MX53_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, MX53_GPIO_PAD_CTRL),
+ MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
+ MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
/* FEC PHY GPIO functions */
MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
printf("\n");
}
-static void print_cpuinfo(void)
+static void tx53_print_cpuinfo(void)
{
u32 cpurev;
int board_early_init_f(void)
{
+ struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
+
gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
- mxc_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
+ imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
+ writel(0xffcf0fff, &ccm_regs->CCGR0);
+ writel(0x000fffc3, &ccm_regs->CCGR1);
+ writel(0x033c0000, &ccm_regs->CCGR2);
+ writel(0x000000ff, &ccm_regs->CCGR3);
+ writel(0x00000000, &ccm_regs->CCGR4);
+ writel(0x00fff033, &ccm_regs->CCGR5);
+ writel(0x0f00030f, &ccm_regs->CCGR6);
+ writel(0xfff00000, &ccm_regs->CCGR7);
+ writel(0x00000000, &ccm_regs->cmeor);
+
return 0;
}
}
#ifdef CONFIG_CMD_MMC
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = mmc->priv;
-
- if (cfg->cd_gpio < 0)
- return cfg->cd_gpio;
+static const iomux_v3_cfg_t mmc0_pads[] = {
+ MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
+ /* SD1 CD */
+ MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
+};
- return !gpio_get_value(cfg->cd_gpio);
-}
+static const iomux_v3_cfg_t mmc1_pads[] = {
+ MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
+ /* SD2 CD */
+ MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
+};
-static struct fsl_esdhc_cfg esdhc_cfg[] = {
+static struct tx53_esdhc_cfg {
+ const iomux_v3_cfg_t *pads;
+ int num_pads;
+ struct fsl_esdhc_cfg cfg;
+ int cd_gpio;
+} tx53_esdhc_cfg[] = {
{
- .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
- .no_snoop = 1,
+ .pads = mmc0_pads,
+ .num_pads = ARRAY_SIZE(mmc0_pads),
+ .cfg = {
+ .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
+ .max_bus_width = 4,
+ },
.cd_gpio = IMX_GPIO_NR(3, 24),
- .wp_gpio = -EINVAL,
},
{
- .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
- .no_snoop = 1,
+ .pads = mmc1_pads,
+ .num_pads = ARRAY_SIZE(mmc1_pads),
+ .cfg = {
+ .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
+ .max_bus_width = 4,
+ },
.cd_gpio = IMX_GPIO_NR(3, 25),
- .wp_gpio = -EINVAL,
},
};
-static const iomux_v3_cfg_t mmc0_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, TX53_SDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, TX53_SDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, TX53_SDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, TX53_SDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, TX53_SDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, TX53_SDHC_PAD_CTRL),
- /* SD1 CD */
- NEW_PAD_CTRL(MX53_PAD_EIM_D24__GPIO3_24, MX53_GPIO_PAD_CTRL),
-};
+#define to_tx53_esdhc_cfg(p) container_of(p, struct tx53_esdhc_cfg, cfg)
-static const iomux_v3_cfg_t mmc1_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, TX53_SDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, TX53_SDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, TX53_SDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, TX53_SDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, TX53_SDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, TX53_SDHC_PAD_CTRL),
- /* SD2 CD */
- NEW_PAD_CTRL(MX53_PAD_EIM_D25__GPIO3_25, MX53_GPIO_PAD_CTRL),
-};
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
-static struct {
- const iomux_v3_cfg_t *pads;
- int count;
-} mmc_pad_config[] = {
- { mmc0_pads, ARRAY_SIZE(mmc0_pads), },
- { mmc1_pads, ARRAY_SIZE(mmc1_pads), },
-};
+ if (cfg->cd_gpio < 0)
+ return cfg->cd_gpio;
+
+ debug("SD card %d is %spresent\n",
+ cfg - tx53_esdhc_cfg,
+ gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
+ return !gpio_get_value(cfg->cd_gpio);
+}
int board_mmc_init(bd_t *bis)
{
int i;
- for (i = 0; i < ARRAY_SIZE(esdhc_cfg); i++) {
+ for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
struct mmc *mmc;
+ struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
+ int ret;
if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
break;
- mxc_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads,
- mmc_pad_config[i].count);
- fsl_esdhc_initialize(bis, &esdhc_cfg[i]);
+ imx_iomux_v3_setup_multiple_pads(cfg->pads,
+ cfg->num_pads);
+ cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ fsl_esdhc_initialize(bis, &cfg->cfg);
+
+ ret = gpio_request_one(cfg->cd_gpio,
+ GPIOF_INPUT, "MMC CD");
+ if (ret) {
+ printf("Error %d requesting GPIO%d_%d\n",
+ ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
+ continue;
+ }
mmc = find_mmc_device(i);
if (mmc == NULL)
{
int ret;
unsigned char mac[ETH_ALEN];
- char mac_str[ETH_ALEN * 3] = "";
/* delay at least 21ms for the PHY internal POR signal to deassert */
udelay(22000);
}
imx_get_mac_from_fuse(0, mac);
- snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
- setenv("ethaddr", mac_str);
+ eth_setenv_enetaddr("ethaddr", mac);
+ printf("MAC addr from fuse: %pM\n", mac);
return ret;
}
MX53_PAD_EIM_A18__GPIO2_20,
/* I2C bus on DIMM pins 40/41 */
- NEW_PAD_CTRL(MX53_PAD_GPIO_6__I2C3_SDA, MX53_GPIO_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_GPIO_3__I2C3_SCL, MX53_GPIO_PAD_CTRL),
+ MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
+ MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
/* TSC200x PEN IRQ */
- NEW_PAD_CTRL(MX53_PAD_EIM_D26__GPIO3_26, MX53_GPIO_PAD_CTRL),
+ MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
/* EDT-FT5x06 Polytouch panel */
- NEW_PAD_CTRL(MX53_PAD_NANDF_CS2__GPIO6_15, MX53_GPIO_PAD_CTRL), /* IRQ */
- NEW_PAD_CTRL(MX53_PAD_EIM_A16__GPIO2_22, MX53_GPIO_PAD_CTRL), /* RESET */
- NEW_PAD_CTRL(MX53_PAD_EIM_A17__GPIO2_21, MX53_GPIO_PAD_CTRL), /* WAKE */
+ MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
+ MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
+ MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
/* USBH1 */
- NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31, MX53_GPIO_PAD_CTRL), /* VBUSEN */
- NEW_PAD_CTRL(MX53_PAD_EIM_D30__GPIO3_30, MX53_GPIO_PAD_CTRL), /* OC */
+ MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
+ MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
/* USBOTG */
MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
MX53_PAD_GPIO_8__GPIO1_8, /* OC */
/* DS1339 Interrupt */
- NEW_PAD_CTRL(MX53_PAD_DI0_PIN4__GPIO4_20, MX53_GPIO_PAD_CTRL),
+ MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
};
static const struct gpio stk5_gpios[] = {
.vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
};
-static struct fb_videomode tx53_fb_mode = {
- /* Standard VGA timing */
- .name = "VGA",
- .refresh = 60,
- .xres = 640,
- .yres = 480,
- .pixclock = KHZ2PICOS(25175),
- .left_margin = 48,
- .hsync_len = 96,
- .right_margin = 16,
- .upper_margin = 31,
- .vsync_len = 2,
- .lower_margin = 12,
- .sync = FB_SYNC_CLK_LAT_FALL,
- .vmode = FB_VMODE_NONINTERLACED,
+static struct fb_videomode tx53_fb_modes[] = {
+ {
+ /* Standard VGA timing */
+ .name = "VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ETV570 640 x 480 display. Syncs low active,
+ * DE high active, 115.2 mm x 86.4 mm display area
+ * VGA compatible timing
+ */
+ .name = "ETV570",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 114,
+ .hsync_len = 30,
+ .right_margin = 16,
+ .upper_margin = 32,
+ .vsync_len = 3,
+ .lower_margin = 10,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0350G0DH6 320 x 240 display.
+ * 70.08 mm x 52.56 mm display area.
+ */
+ .name = "ET0350",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6500),
+ .left_margin = 68 - 34,
+ .hsync_len = 34,
+ .right_margin = 20,
+ .upper_margin = 18 - 3,
+ .vsync_len = 3,
+ .lower_margin = 4,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0430G0DH6 480 x 272 display.
+ * 95.04 mm x 53.856 mm display area.
+ */
+ .name = "ET0430",
+ .refresh = 60,
+ .xres = 480,
+ .yres = 272,
+ .pixclock = KHZ2PICOS(9000),
+ .left_margin = 2,
+ .hsync_len = 41,
+ .right_margin = 2,
+ .upper_margin = 2,
+ .vsync_len = 10,
+ .lower_margin = 2,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0500G0DH6 800 x 480 display.
+ * 109.6 mm x 66.4 mm display area.
+ */
+ .name = "ET0500",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ETQ570G0DH6 320 x 240 display.
+ * 115.2 mm x 86.4 mm display area.
+ */
+ .name = "ETQ570",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6400),
+ .left_margin = 38,
+ .hsync_len = 30,
+ .right_margin = 30,
+ .upper_margin = 16, /* 15 according to datasheet */
+ .vsync_len = 3, /* TVP -> 1>x>5 */
+ .lower_margin = 4, /* 4.5 according to datasheet */
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* Emerging ET0700G0DH6 800 x 480 display.
+ * 152.4 mm x 91.44 mm display area.
+ */
+ .name = "ET0700",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+ {
+ /* unnamed entry for assigning parameters parsed from 'video_mode' string */
+ .refresh = 60,
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
};
-void *lcd_base; /* Start of framebuffer memory */
-void *lcd_console_address; /* Start of console buffer */
-
-int lcd_line_length;
-int lcd_color_fg;
-int lcd_color_bg;
-
-short console_col;
-short console_row;
-
-void lcd_initcolregs(void)
-{
-}
-
-void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
-{
-}
-
static int lcd_enabled = 1;
void lcd_enable(void)
*/
lcd_is_enabled = 0;
- karo_load_splashimage(1);
if (lcd_enabled) {
+ karo_load_splashimage(1);
+
debug("Switching LCD on\n");
gpio_set_value(TX53_LCD_PWR_GPIO, 1);
udelay(100);
}
}
-void mxcfb_disable(void);
-
void lcd_disable(void)
{
- mxcfb_disable();
+ if (lcd_enabled) {
+ printf("Disabling LCD\n");
+ ipuv3_fb_shutdown();
+ }
}
void lcd_panel_disable(void)
static const iomux_v3_cfg_t stk5_lcd_pads[] = {
/* LCD RESET */
- NEW_PAD_CTRL(MX53_PAD_EIM_D29__GPIO3_29, MX53_GPIO_PAD_CTRL),
+ MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
/* LCD POWER_ENABLE */
- NEW_PAD_CTRL(MX53_PAD_EIM_EB3__GPIO2_31, MX53_GPIO_PAD_CTRL),
+ MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
/* LCD Backlight (PWM) */
- NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, MX53_GPIO_PAD_CTRL),
+ MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
/* Display */
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
char *vm;
unsigned long val;
int refresh = 60;
- struct fb_videomode *p = &tx53_fb_mode;
+ struct fb_videomode *p = &tx53_fb_modes[0];
+ struct fb_videomode fb_mode;
int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
int pix_fmt = 0;
+ ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
+ unsigned long di_clk_rate = 65000000;
if (!lcd_enabled) {
debug("LCD disabled\n");
if (tstc() || (wrsr & WRSR_TOUT)) {
debug("Disabling LCD\n");
lcd_enabled = 0;
+ setenv("splashimage", NULL);
return;
}
+ karo_fdt_move_fdt();
+
vm = getenv("video_mode");
if (vm == NULL) {
debug("Disabling LCD\n");
lcd_enabled = 0;
return;
}
+ if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
+ p = &fb_mode;
+ debug("Using video mode from FDT\n");
+ vm += strlen(vm);
+ if (fb_mode.xres < panel_info.vl_col)
+ panel_info.vl_col = fb_mode.xres;
+ if (fb_mode.yres < panel_info.vl_row)
+ panel_info.vl_row = fb_mode.yres;
+ }
+ if (p->name != NULL)
+ debug("Trying compiled-in video modes\n");
+ while (p->name != NULL) {
+ if (strcmp(p->name, vm) == 0) {
+ debug("Using video mode: '%s'\n", p->name);
+ vm += strlen(vm);
+ break;
+ }
+ p++;
+ }
+ if (*vm != '\0')
+ debug("Trying to decode video_mode: '%s'\n", vm);
while (*vm != '\0') {
if (*vm >= '0' && *vm <= '9') {
char *end;
yres_set = 1;
} else if (!bpp_set) {
switch (val) {
+ case 32:
case 24:
if (pix_fmt == IPU_PIX_FMT_LVDS666)
pix_fmt = IPU_PIX_FMT_LVDS888;
if (!pix_fmt) {
char *tmp;
- if (strncmp(vm, "LVDS", 4) == 0)
+ if (strncmp(vm, "LVDS", 4) == 0) {
pix_fmt = IPU_PIX_FMT_LVDS666;
- else
+ di_clk_parent = DI_PCLK_LDB;
+ } else {
pix_fmt = IPU_PIX_FMT_RGB24;
+ }
tmp = strchr(vm, ':');
if (tmp)
vm = tmp;
vm++;
}
}
- switch (color_depth) {
- case 8:
- panel_info.vl_bpix = 3;
- break;
-
- case 16:
- panel_info.vl_bpix = 4;
- break;
-
- case 18:
- case 24:
- panel_info.vl_bpix = 5;
+ if (p->xres == 0 || p->yres == 0) {
+ printf("Invalid video mode: %s\n", getenv("video_mode"));
+ lcd_enabled = 0;
+ printf("Supported video modes are:");
+ for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
+ printf(" %s", p->name);
+ }
+ printf("\n");
+ return;
}
- lcd_line_length = NBITS(panel_info.vl_bpix) / 8 * panel_info.vl_col;
p->pixclock = KHZ2PICOS(refresh *
(p->xres + p->left_margin + p->right_margin + p->hsync_len) *
PICOS2KHZ(p->pixclock) / 1000,
PICOS2KHZ(p->pixclock) % 1000);
+ if (p != &fb_mode) {
+ int ret;
+ char *modename = getenv("video_mode");
+
+ printf("Creating new display-timing node from '%s'\n",
+ modename);
+ ret = karo_fdt_create_fb_mode(working_fdt, modename, p);
+ if (ret)
+ printf("Failed to create new display-timing node from '%s': %d\n",
+ modename, ret);
+ }
+
gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
- mxc_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
+ imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
ARRAY_SIZE(stk5_lcd_pads));
debug("Initializing FB driver\n");
writel(0x21, IOMUXC_BASE_ADDR + 8);
}
if (pix_fmt != IPU_PIX_FMT_RGB24) {
- struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+ struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* enable LDB & DI0 clock */
writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
&ccm_regs->CCGR6);
}
- mx5_fb_init(p, 0, pix_fmt, 1 << panel_info.vl_bpix);
-
if (karo_load_splashimage(0) == 0) {
+ int ret;
+
+ gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3M;
+
debug("Initializing LCD controller\n");
- video_hw_init();
+ ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
+ if (ret) {
+ printf("Failed to initialize FB driver: %d\n", ret);
+ lcd_enabled = 0;
+ }
} else {
debug("Skipping initialization of LCD controller\n");
}
static void stk5_board_init(void)
{
gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
- mxc_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
+ imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
}
static void stk5v3_board_init(void)
gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
"Flexcan Transceiver");
- mxc_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
+ imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
}
static void tx53_set_cpu_clock(void)
int checkboard(void)
{
- print_cpuinfo();
+ tx53_print_cpuinfo();
printf("Board: Ka-Ro TX53-xx3%s\n",
TX53_MOD_SUFFIX);
static inline void tx53_fixup_rtc(void *blob)
{
}
-#endif
+#endif /* CONFIG_SYS_TX53_HWREV_2 */
void ft_board_setup(void *blob, bd_t *bd)
{
fdt_fixup_ethernet(blob);
karo_fdt_fixup_touchpanel(blob);
- karo_fdt_fixup_usb_otg(blob);
+ karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");
tx53_fixup_flexcan(blob);
tx53_fixup_rtc(blob);
+ karo_fdt_update_fb_mode(blob, getenv("video_mode"));
}
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
projects / karo-tx-uboot.git / blobdiff