karo: tx6: add support for TX6 HW Rev. 3

[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S

diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S
index d6d062a3a7d7901f20302915c3166d0c41ea4672..11189e11c1d2147746519f94c087721fac12b96c 100644 (file)
--- a/board/karo/tx6/lowlevel_init.S
+++ b/board/karo/tx6/lowlevel_init.S
@@ -352,18 +352,14 @@ plugin:
 ivt_end:
 #define DCD_VERSION    0x40
 
-#define CLKCTL_CCGR0   0x68
-#define CLKCTL_CCGR1   0x6c
-#define CLKCTL_CCGR2   0x70
-#define CLKCTL_CCGR3   0x74
-#define CLKCTL_CCGR4   0x78
-#define CLKCTL_CCGR5   0x7c
-#define CLKCTL_CCGR6   0x80
-#define CLKCTL_CCGR7   0x84
-#define CLKCTL_CMEOR   0x88
-
-#define DDR_SEL_VAL    3
-#define DSE_VAL                6
+#define DDR_SEL_VAL    3 /* DDR3 */
+#if PHYS_SDRAM_1_WIDTH == 16
+#define DSE1_VAL       6 /* Drive Strength for DATA lines */
+#define DSE2_VAL       6 /* Drive Strength for ADDR/CMD lines */
+#else
+#define DSE1_VAL       6 /* Drive Strength for DATA lines */
+#define DSE2_VAL       6 /* Drive Strength for ADDR/CMD lines */
+#endif
 #define ODT_VAL                2
 #define DDR_PKE_VAL    0
 
@@ -377,18 +373,19 @@ ivt_end:
 #define PUS_SHIFT      14
 
 #define DDR_SEL_MASK   (DDR_SEL_VAL << DDR_SEL_SHIFT)
-#define DDR_MODE_MASK  (1 << DDR_MODE_SHIFT)
-#define DSE_MASK       (DSE_VAL << DSE_SHIFT)
+#define DDR_MODE_MASK  (1 << DDR_MODE_SHIFT) /* differential input mode */
+#define DSE1_MASK      (DSE1_VAL << DSE_SHIFT)
+#define DSE2_MASK      (DSE2_VAL << DSE_SHIFT)
 #define ODT_MASK       (ODT_VAL << ODT_SHIFT)
 #define DDR_PKE_MASK   (DDR_PKE_VAL << PKE_SHIFT)
 
-#define DQM_MASK       (DDR_MODE_MASK | DSE_MASK)
-#define SDQS_MASK      DSE_MASK
-#define SDODT_MASK     (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
-#define SDCLK_MASK     (DDR_MODE_MASK | DSE_MASK)
+#define DQM_MASK       (DDR_MODE_MASK | DSE2_MASK)
+#define SDQS_MASK      DSE2_MASK
+#define SDODT_MASK     (DSE2_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define SDCLK_MASK     (DDR_MODE_MASK | DSE2_MASK)
 #define SDCKE_MASK     ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
-#define DDR_ADDR_MASK  0
-#define DDR_CTRL_MASK  (DDR_MODE_MASK | DSE_MASK)
+#define DDR_ADDR_MASK  (ODT_MASK | DDR_MODE_MASK)
+#define DDR_CTRL_MASK  (DDR_MODE_MASK | DSE2_MASK)
 
 #define MMDC1_MDCTL                            0x021b0000
 #define MMDC1_MDPDC                            0x021b0004
@@ -568,7 +565,7 @@ ivt_end:
 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
 #endif
 
-#ifdef CONFIG_MX6DL
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
 #define IOMUXC_GPR1                            0x020e0004
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17           0x020e0218
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7                0x020e0330
@@ -755,16 +752,16 @@ dcd_hdr:
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
        /* DRAM_B[0..7]DS */
-       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE_MASK)
-       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE_MASK)
-       MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK)
-       MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK)
-       MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK)
-       MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK)
-       MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK)
-       MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE_MASK)
+       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE1_MASK)
+       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE1_MASK)
+       MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE1_MASK)
+       MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE1_MASK)
+       MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE1_MASK)
+       MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE1_MASK)
+       MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE1_MASK)
+       MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE1_MASK)
        /* ADDDS */
-       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE_MASK)
+       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE2_MASK)
        /* DDRMODE_CTL */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
        /* DDRPKE */
@@ -772,7 +769,7 @@ dcd_hdr:
        /* DDRMODE */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
        /* CTLDS */
-       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE_MASK)
+       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE2_MASK)
        /* DDR_TYPE */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
        /* DDRPK */
@@ -929,7 +926,8 @@ dcd_hdr:
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
        MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
        MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f)
+       MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000013)
+       MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f)
        MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f)
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
 #else /* DO_DDR_CALIB */
@@ -940,7 +938,8 @@ dcd_hdr:
        /* Write delay calibration */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
        MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
+       MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000013)
+       MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
 #if PHYS_SDRAM_1_WIDTH == 64
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)