karo: tx6: implement secure boot support

[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S

diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S
index 3161c227f3ae346476425cbd389f7fd3a8bbd3b3..34a7b285e2178354ad3f95fe1dcb9330a65af212 100644 (file)
--- a/board/karo/tx6/lowlevel_init.S
+++ b/board/karo/tx6/lowlevel_init.S
@@ -1,5 +1,7 @@
 #include <config.h>
+#include <asm-offsets.h>
 #include <configs/tx6.h>
+#include <linux/linkage.h>
 #include <asm/arch/imx-regs.h>
 #include <generated/asm-offsets.h>
 
@@ -87,6 +89,8 @@ dcd_start:
        .error  "DCD too large!"
        .endif
 dcd_end:
+       .section ".pad"
+       .section ".text"
        .endm
 
 #define MXC_DCD_CMD_WRT(type, flags)                                   \
@@ -329,6 +333,7 @@ CK_MAX      tCKSRE, NS_TO_CK(10), 5, 0, 7
                                (tODTLon << 12) |       \
                                (tODTLoff << 4))
 
+       .section ".ivt"
 ivt_header:
        .word   CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
 app_start_addr:
@@ -341,12 +346,16 @@ boot_data_ptr:
 self_ptr:
        .word   ivt_header
 app_code_csf:
+#ifdef CONFIG_SECURE_BOOT
+       .word   __csf_data
+#else
        .word   0x0
+#endif
        .word   0x0
 boot_data:
-       .long   _start
+       .long   CONFIG_SYS_TEXT_BASE
 image_len:
-       .long   CONFIG_U_BOOT_IMG_SIZE
+       .long   __uboot_img_len
 plugin:
        .word   0
 ivt_end:
@@ -470,7 +479,7 @@ ivt_end:
 #define MMDC2_MPSWDRDR7                                0x021b48b4
 #endif
 
-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q
 #define IOMUXC_GPR1                            0x020e0004
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17           0x020e024c
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7                0x020e02a8
@@ -565,7 +574,7 @@ ivt_end:
 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
 #endif
 
-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
 #define IOMUXC_GPR1                            0x020e0004
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17           0x020e0218
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7                0x020e0330
@@ -681,7 +690,7 @@ dcd_hdr:
        /* UART1 pad config */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7,        0x00000001)        /* UART1 TXD */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6,        0x00000001)        /* UART1 RXD */
-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q
        MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003)        /* UART1 RXD INPUT_SEL */
 #else
        MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002)        /* UART1 RXD INPUT_SEL */
@@ -782,7 +791,7 @@ dcd_hdr:
        /* DDRHYS */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
 
-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q
        /* TERM_CTL[0..7] */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)