karo: tx6: fix definition of IOMUXC_SW_PAD_CTL_GRP_DDRPK for i.MX6DL

[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S

diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S
index 7d38c6889fd12d60245b4ca5b8a1ae4863546a3c..3e1f7b73c0b66bb83da70a0fee478399a4b57302 100644 (file)
--- a/board/karo/tx6/lowlevel_init.S
+++ b/board/karo/tx6/lowlevel_init.S
@@ -351,6 +351,7 @@ ivt_end:
 #define DDR_SEL_VAL    3
 #define DSE_VAL                6
 #define ODT_VAL                2
+#define DDR_PKE_VAL    0
 
 #define DDR_SEL_SHIFT  18
 #define DDR_MODE_SHIFT 17
@@ -365,6 +366,7 @@ ivt_end:
 #define DDR_MODE_MASK  (1 << DDR_MODE_SHIFT)
 #define DSE_MASK       (DSE_VAL << DSE_SHIFT)
 #define ODT_MASK       (ODT_VAL << ODT_SHIFT)
+#define DDR_PKE_MASK   (DDR_PKE_VAL << PKE_SHIFT)
 
 #define DQM_MASK       (DDR_MODE_MASK | DSE_MASK)
 #define SDQS_MASK      DSE_MASK
@@ -400,7 +402,6 @@ ivt_end:
 #define MMDC1_MPDGCTRL0                                0x021b083c
 #define MMDC1_MPDGCTRL1                                0x021b0840
 #define MMDC1_MPDGDLST0                                0x021b0844
-#define MMDC1_MPWRDLST                         0x021b0854
 #define MMDC1_MPRDDLCTL                                0x021b0848
 #define MMDC1_MPRDDLST                         0x021b084c
 #define MMDC1_MPWRDLCTL                                0x021b0850
@@ -624,7 +625,7 @@ ivt_end:
 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS            0x020e074c
 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL      0x020e0750
 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE           0x020e0754
-#define IOMUXC_SW_PAD_CTL_GRP_DDRPK            0x020e0754
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPK            0x020e0758
 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS           0x020e075c
 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE          0x020e0760
 #define IOMUXC_SW_PAD_CTL_GRP_B0DS             0x020e0784
@@ -753,7 +754,7 @@ dcd_hdr:
        /* DDRMODE_CTL */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
        /* DDRPKE */
-       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000)
+       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, DDR_PKE_MASK)
        /* DDRMODE */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
        /* CTLDS */
@@ -844,7 +845,6 @@ dcd_hdr:
 
        MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
 
-#ifndef DO_WL_CALIB
 #define WL_DLY_DQS_VAL 30
 #define WL_DLY_DQS0    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS1    (WL_DLY_DQS_VAL + 0)
@@ -854,28 +854,11 @@ dcd_hdr:
 #define WL_DLY_DQS5    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS6    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS7    (WL_DLY_DQS_VAL + 0)
-#endif
        /* Write leveling */
-       MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
-#ifdef DO_WL_CALIB
-       MXC_DCD_ITEM(MMDC1_MDSCR, 0x00808231) /* MRS: start write leveling */
-       MXC_DCD_ITEM(MMDC1_MPWLGCR, 0x00000001) /* initiate Write leveling */
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000001)
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000f00)
-#if PHYS_SDRAM_1_WIDTH == 64
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000001)
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000f00)
-#endif /* PHYS_SDRAM_1_WIDTH == 64 */
-#else
        MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
        MXC_DCD_ITEM(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
        MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
        MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
-#endif /* DO_WL_CALIB */
-
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-       MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
-
 
        /* DQS gating calibration */
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */