.endm
#define MXC_DCD_ITEM(addr, val) mxc_dcd_item addr, val
+#if PHYS_SDRAM_1_WIDTH == 64
+#define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item addr, val
+#define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
+#else
+#define MXC_DCD_ITEM_64(addr, val)
+#define MXC_DCD_CMD_CHK_64(type, flags, addr, mask)
+#endif
#define MXC_DCD_CMD_SZ_BYTE 1
#define MXC_DCD_CMD_SZ_SHORT 2
.word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
-#define MXC_DCD_CMD_NOP \
+#define MXC_DCD_CMD_NOP() \
.word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+#define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10)
.macro CK_VAL, name, clks, offs, max
.iflt \clks - \offs
#define SDRAM_BURST_LENGTH 8
#define RALAT 5
#define WALAT 0
-#define BI_ON 1
-#define ADDR_MIRROR 1
+#define BI_ON 0
+#define ADDR_MIRROR 0
#define DDR_TYPE MDMISC_DDR_TYPE_DDR3
-/* 512/1024MiB SDRAM: NT5CB128M16P-CG */
+/* 512/1024MiB SDRAM: NT5CB128M16FP-DII */
+#if SDRAM_CLK > 666 && SDRAM_CLK <= 800
+#define CL_VAL 11
+#define CWL_VAL 8
+#elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
+#define CL_VAL 9 // or 10
+#define CWL_VAL 7
+#elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
+#define CL_VAL 7 // or 8
+#define CWL_VAL 6
+#elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
+#define CL_VAL 6
+#define CWL_VAL 5
+#elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
+#define CL_VAL 5
+#define CWL_VAL 5
+#else
+#error SDRAM clock out of range: 303 .. 800
+#endif
+
/* MDCFG0 0x0c */
NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
-CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
-CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
+CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
+CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
-NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
-CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */
+NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */
/* MDCFG1 0x10 */
-NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
-NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tRCD, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */
+CK_VAL tRP, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */
NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
-NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
-CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
+CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) */ /* 37.5 */
+CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
-CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */
+CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */
/* MDCFG2 0x14 */
CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
-CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
-CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
-CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) */
/* MDOR 0x30 */
CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
/* MDOTC 0x08 */
-NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
-NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */
+CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */
CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
-CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */
-CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tODTLon tCWL, 0, 7 /* clks - 1 (0..7) */ /* CWL+AL-2 */
+CK_VAL tODTLoff tCWL, 0, 31 /* clks - 1 (0..31) */ /* CWL+AL-2 */
/* MDPDC 0x04 */
-CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7
+CK_MAX tCKE, NS_TO_CK(5), 3, 1, 7
CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
(PWDT << 8) \
)
-#define ROW_ADDR_BITS 14
-#define COL_ADDR_BITS 10
+#define ROW_ADDR_BITS 14
+#define COL_ADDR_BITS 10
+
+#define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
+#define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
+#define DLL_DISABLE 0
.iflt tWR - 7
- .set mr0_val, ((1 << 8) /* DLL Reset */ | \
- ((tWR + 1 - 4) << 9) | \
- (((tCL + 3) - 4) << 4))
+ .set mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ | \
+ (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
+ ((tWR + 1 - 4) << 9) | \
+ ((((tCL + 3) - 4) & 0x7) << 4) | \
+ ((((tCL + 3) - 4) & 0x8) >> 1))
.else
- .set mr0_val, ((1 << 8) /* DLL Reset */ | \
+ .set mr0_val, ((1 << 8) /* DLL Reset */ | \
+ (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
(((tWR + 1) / 2) << 9) | \
- (((tCL + 3) - 4) << 4))
+ ((((tCL + 3) - 4) & 0x7) << 4) | \
+ ((((tCL + 3) - 4) & 0x8) >> 1))
.endif
+#define mr1_val ( \
+ ((Rtt_Nom & 1) << 2) | \
+ (((Rtt_Nom >> 1) & 1) << 6) | \
+ (((Rtt_Nom >> 2) & 1) << 9) | \
+ (DLL_DISABLE << 0) | \
+ 0)
+#define mr2_val ( \
+ (Rtt_WR << 9) /* dynamic ODT */ | \
+ (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
+ (1 << 6) | /* ASR: Automatic Self Refresh */ \
+ (((tCWL + 2) - 5) << 3) | \
+ 0)
+#define mr3_val 0
+
#define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
- (1 << 15) /* CON REQ */ | \
+ (1 << 15) /* CON_REQ */ | \
(3 << 4) /* MRS command */ | \
((cs) << 3) | \
- ((mr) << 0))
-
-#define mr1_val 0x0040
-#define mr2_val 0x0408
+ ((mr) << 0) | \
+ 0)
#define MDCFG0_VAL ( \
(tRFC << 24) | \
(tWTR << 3) | \
(tRRD << 0))
-#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
+#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
-#if PHYS_SDRAM_1_WIDTH == 64
-#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
- ((COL_ADDR_BITS - 9) << 20) | \
- (BURST_LEN << 19) | \
- (2 << 16) | /* SDRAM bus width */ \
- ((-1) << (32 - BANK_ADDR_BITS)))
-#else
-#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
- ((COL_ADDR_BITS - 9) << 20) | \
- (BURST_LEN << 19) | \
- (1 << 16) | /* SDRAM bus width */ \
- ((-1) << (32 - BANK_ADDR_BITS)))
-#endif
+#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
+ ((COL_ADDR_BITS - 9) << 20) | \
+ (BURST_LEN << 19) | \
+ ((PHYS_SDRAM_1_WIDTH / 32) << 16) | \
+ ((-1) << (32 - BANK_ADDR_BITS)))
+
+#define MDMISC_VAL ((ADDR_MIRROR << 19) | \
+ (WALAT << 16) | \
+ (BI_ON << 12) | \
+ (0x3 << 9) | \
+ (RALAT << 6) | \
+ (DDR_TYPE << 3))
+
+#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
+
+#define MDOTC_VAL ((tAOFPD << 27) | \
+ (tAONPD << 24) | \
+ (tANPD << 20) | \
+ (tAXPD << 16) | \
+ (tODTLon << 12) | \
+ (tODTLoff << 4))
-#define MDMISC_VAL ((ADDR_MIRROR << 19) | \
- (WALAT << 16) | \
- (BI_ON << 12) | \
- (0x3 << 9) | \
- (RALAT << 6) | \
- (DDR_TYPE << 3))
-
-#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
-
-#define MDOTC_VAL ((tAOFPD << 27) | \
- (tAONPD << 24) | \
- (tANPD << 20) | \
- (tAXPD << 16) | \
- (tODTLon << 12) | \
- (tODTLoff << 4))
-
-fcb_start:
- b _start
- .org 0x400
ivt_header:
- .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
+ .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
app_start_addr:
- .long _start
- .long 0x0
+ .long _start
+ .long 0x0
dcd_ptr:
- .long dcd_hdr
+ .long dcd_hdr
boot_data_ptr:
- .word boot_data
+ .word boot_data
self_ptr:
- .word ivt_header
+ .word ivt_header
app_code_csf:
- .word 0x0
- .word 0x0
+ .word 0x0
+ .word 0x0
boot_data:
- .long fcb_start
+ .long _start
image_len:
- .long CONFIG_U_BOOT_IMG_SIZE
+ .long CONFIG_U_BOOT_IMG_SIZE
plugin:
- .word 0
+ .word 0
ivt_end:
#define DCD_VERSION 0x40
#define MMDC1_MAPSR 0x021b0404
#define MMDC1_MPZQHWCTRL 0x021b0800
#define MMDC1_MPWLGCR 0x021b0808
+#define MMDC1_MPWLDECTRL0 0x021b080c
+#define MMDC1_MPWLDECTRL1 0x021b0810
+#define MMDC1_MPWLDLST 0x021b0814
#define MMDC1_MPODTCTRL 0x021b0818
#define MMDC1_MPRDDQBY0DL 0x021b081c
#define MMDC1_MPRDDQBY1DL 0x021b0820
#define MMDC1_MPRDDQBY2DL 0x021b0824
#define MMDC1_MPRDDQBY3DL 0x021b0828
#define MMDC1_MPDGCTRL0 0x021b083c
+#define MMDC1_MPDGCTRL1 0x021b0840
+#define MMDC1_MPDGDLST0 0x021b0844
+#define MMDC1_MPWRDLST 0x021b0854
#define MMDC1_MPRDDLCTL 0x021b0848
+#define MMDC1_MPRDDLST 0x021b084c
#define MMDC1_MPWRDLCTL 0x021b0850
+#define MMDC1_MPWRDLST 0x021b0854
#define MMDC1_MPRDDLHWCTL 0x021b0860
#define MMDC1_MPWRDLHWCTL 0x021b0864
#define MMDC1_MPPDCMPR2 0x021b0890
+#define MMDC1_MPSWDRDR0 0x021b0898
+#define MMDC1_MPSWDRDR1 0x021b089c
+#define MMDC1_MPSWDRDR2 0x021b08a0
+#define MMDC1_MPSWDRDR3 0x021b08a4
+#define MMDC1_MPSWDRDR4 0x021b08a8
+#define MMDC1_MPSWDRDR5 0x021b08ac
+#define MMDC1_MPSWDRDR6 0x021b08b0
+#define MMDC1_MPSWDRDR7 0x021b08b4
#define MMDC1_MPMUR0 0x021b08b8
-#define MMDC2_MPZQHWCTRL 0x021b4800
+
+#if PHYS_SDRAM_1_WIDTH == 64
+#define MMDC2_MDPDC 0x021b4004
#define MMDC2_MPWLGCR 0x021b4808
+#define MMDC2_MPWLDECTRL0 0x021b480c
+#define MMDC2_MPWLDECTRL1 0x021b4810
+#define MMDC2_MPWLDLST 0x021b4814
#define MMDC2_MPODTCTRL 0x021b4818
#define MMDC2_MPRDDQBY0DL 0x021b481c
#define MMDC2_MPRDDQBY1DL 0x021b4820
#define MMDC2_MPRDDQBY2DL 0x021b4824
#define MMDC2_MPRDDQBY3DL 0x021b4828
#define MMDC2_MPDGCTRL0 0x021b483c
+#define MMDC2_MPDGCTRL1 0x021b4840
+#define MMDC2_MPDGDLST0 0x021b4844
#define MMDC2_MPRDDLCTL 0x021b4848
+#define MMDC2_MPRDDLST 0x021b484c
#define MMDC2_MPWRDLCTL 0x021b4850
+#define MMDC2_MPWRDLST 0x021b4854
#define MMDC2_MPRDDLHWCTL 0x021b4860
#define MMDC2_MPWRDLHWCTL 0x021b4864
-#define MMDC2_MPMUR0 0x021b48b8
+#define MMDC2_MPRDDLHWST0 0x021b4868
+#define MMDC2_MPRDDLHWST1 0x021b486c
+#define MMDC2_MPWRDLHWST0 0x021b4870
+#define MMDC2_MPWRDLHWST1 0x021b4874
+#define MMDC2_MPWLHWERR 0x021b4878
+#define MMDC2_MPDGHWST0 0x021b487c
+#define MMDC2_MPDGHWST1 0x021b4880
+#define MMDC2_MPDGHWST2 0x021b4884
+#define MMDC2_MPDGHWST3 0x021b4888
+#define MMDC2_MPSWDAR0 0x021b4894
+#define MMDC2_MPSWDRDR0 0x021b4898
+#define MMDC2_MPSWDRDR1 0x021b489c
+#define MMDC2_MPSWDRDR2 0x021b48a0
+#define MMDC2_MPSWDRDR3 0x021b48a4
+#define MMDC2_MPSWDRDR4 0x021b48a8
+#define MMDC2_MPSWDRDR5 0x021b48ac
+#define MMDC2_MPSWDRDR6 0x021b48b0
+#define MMDC2_MPSWDRDR7 0x021b48b4
+#endif
#ifdef CONFIG_MX6Q
#define IOMUXC_GPR1 0x020e0004
MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT, 0x00000003) /* UART1 RTS INPUT_SEL */
/* NAND */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE, 0x00000000) /* NANDF_CLE: NANDF_CLE */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, 0x00000000) /* NANDF_ALE: NANDF_ALE */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CMD, 0x00000001) /* SD4_CMD: NANDF_RDn */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CLK, 0x00000001) /* SD4_CLK: NANDF_WRn */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000) /* NANDF_D0: NANDF_D0 */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000) /* NANDF_D1: NANDF_D1 */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000) /* NANDF_D2: NANDF_D2 */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000) /* NANDF_D3: NANDF_D3 */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000) /* NANDF_D4: NANDF_D4 */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000) /* NANDF_D5: NANDF_D5 */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000) /* NANDF_D6: NANDF_D6 */
- MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000) /* NANDF_D7: NANDF_D7 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE, 0x00000000) /* NANDF_CLE: NANDF_CLE */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, 0x00000000) /* NANDF_ALE: NANDF_ALE */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CMD, 0x00000001) /* SD4_CMD: NANDF_RDn */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CLK, 0x00000001) /* SD4_CLK: NANDF_WRn */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000) /* NANDF_D0: NANDF_D0 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000) /* NANDF_D1: NANDF_D1 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000) /* NANDF_D2: NANDF_D2 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000) /* NANDF_D3: NANDF_D3 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000) /* NANDF_D4: NANDF_D4 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000) /* NANDF_D5: NANDF_D5 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000) /* NANDF_D6: NANDF_D6 */
+ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000) /* NANDF_D7: NANDF_D7 */
/* ext. mem CS */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000) /* NANDF_CS2: NANDF_CS2 */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
-#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, DQM_MASK)
-#endif
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, DQM_MASK)
/* DRAM_A[0..15] */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK)
-#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE_MASK)
-#endif
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE_MASK)
/* ADDDS */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE_MASK)
/* DDRMODE_CTL */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
#endif
-
/* SDRAM initialization */
/* MPRDDQBY[0..7]DL */
MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
MXC_DCD_ITEM(MMDC1_MPRDDQBY2DL, 0x33333333)
MXC_DCD_ITEM(MMDC1_MPRDDQBY3DL, 0x33333333)
-#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_ITEM(MMDC2_MPRDDQBY0DL, 0x33333333)
- MXC_DCD_ITEM(MMDC2_MPRDDQBY1DL, 0x33333333)
- MXC_DCD_ITEM(MMDC2_MPRDDQBY2DL, 0x33333333)
- MXC_DCD_ITEM(MMDC2_MPRDDQBY3DL, 0x33333333)
-#endif
+ MXC_DCD_ITEM_64(MMDC2_MPRDDQBY0DL, 0x33333333)
+ MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333)
+ MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333)
+ MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333)
/* MDMISC */
MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
ddr_reset:
MXC_DCD_ITEM(MMDC1_MDOR, MDOR_VAL)
MXC_DCD_ITEM(MMDC1_MDOTC, MDOTC_VAL)
MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_0)
+ MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_0)
MXC_DCD_ITEM(MMDC1_MDASP, (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1) /* MDASP */
/* CS0 MRS: */
MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
- MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00011112) /* MPODTCTRL */
-#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_ITEM(MMDC2_MPODTCTRL, 0x00011112)
-#endif
+ MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222) /* MPODTCTRL */
+ MXC_DCD_ITEM_64(MMDC2_MPODTCTRL, 0x00022222)
/* DDR3 calibration */
MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
/* ZQ calibration */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
-
MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa139002b)
-#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_ITEM(MMDC2_MPZQHWCTRL, 0xa138002b)
-#endif
zq_calib:
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
- /* Write leveling */
MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
-#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_ITEM(MMDC2_MPZQHWCTRL, 0xa1380000)
-#endif
+#ifndef DO_WL_CALIB
+#define WL_DLY_DQS_VAL 30
+#define WL_DLY_DQS0 (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS1 (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS2 (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS3 (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS4 (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS5 (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS6 (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS7 (WL_DLY_DQS_VAL + 0)
+#endif
+ /* Write leveling */
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
+#ifdef DO_WL_CALIB
MXC_DCD_ITEM(MMDC1_MDSCR, 0x00808231) /* MRS: start write leveling */
-
MXC_DCD_ITEM(MMDC1_MPWLGCR, 0x00000001) /* initiate Write leveling */
wl_calib:
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000001)
#if PHYS_SDRAM_1_WIDTH == 64
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000001)
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000f00)
-#endif
+#endif /* PHYS_SDRAM_1_WIDTH == 64 */
+#else
+ MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
+ MXC_DCD_ITEM(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
+ MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
+ MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
+wl_calib:
+#endif /* DO_WL_CALIB */
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset)
- MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
-#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_ITEM(MMDC2_MPZQHWCTRL, 0xa138002b)
-#endif
-
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
+ MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
+
/* DQS gating calibration */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
-#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
-#endif
- MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | (7 << 6) | (3 << 16)) /* RALAT/WALAT max. */
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
+
+ MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
+ MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
+ MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
MXC_DCD_ITEM(MMDC1_MPMUR0, 0x00000800)
-#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_ITEM(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
- MXC_DCD_ITEM(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
- MXC_DCD_ITEM(MMDC2_MPMUR0, 0x00000800)
-#endif
-
MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
dqs_fifo_reset:
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
dqs_calib:
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10000000)
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x00001000)
-#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPDGCTRL0, 0x10000000)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPDGCTRL0, 0x00001000)
-#endif
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
/* DRAM_SDQS[0..7] pad config */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
-#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
-#endif
-
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
+ MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
/* Read delay calibration */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
- MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_RD_DL_EN */
+ MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
+ MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
rd_dl_calib:
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000010)
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000000f)
-#if PHYS_SDRAM_1_WIDTH == 64
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x00000010)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000000f)
-#endif
+ MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x00000010)
+ MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000000f)
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000010)
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000000f)
#if PHYS_SDRAM_1_WIDTH == 64
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib2)
+
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
+ MXC_DCD_ITEM(MMDC2_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
+wr_dl_calib2:
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x00000010)
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000000f)
#endif
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr)
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
- MXC_DCD_ITEM(MMDC1_MDREF, 0x00005800) /* MDREF */
+ MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
MXC_DCD_ITEM(MMDC1_MAPSR, 0x00011006) /* MAPSR */
MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
+ MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_1)
/* MDSCR: Normal operation */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)
projects / karo-tx-uboot.git / blobdiff